;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.4.0 Tue Oct 12 01:21:33 2004

;--------------------------------------------------------
	.module _strcat
	
	.area CSEG
	.area GSINIT
	.area GSFINAL
	.area XINIT
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl _strcat_PARM_2
	.globl _strcat
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area	OSEG    (OVR)
_strcat_sloc0_1_0::
	.ds 2
_strcat_sloc1_1_0::
	.ds 1
_strcat_sloc2_1_0::
	.ds 2
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
_strcat_PARM_2::
	.ds 2
_strcat_dst_1_1::
	.ds 2
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area GSINIT
	.area GSFINAL
	.area GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME
	.area CSEG
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG
;------------------------------------------------------------
;Allocation info for local variables in function 'strcat'
;------------------------------------------------------------
;src                       Allocated with name '_strcat_PARM_2'
;dst                       Allocated with name '_strcat_dst_1_1'
;cp                        Allocated to registers 
;sloc0                     Allocated with name '_strcat_sloc0_1_0'
;sloc1                     Allocated with name '_strcat_sloc1_1_0'
;sloc2                     Allocated with name '_strcat_sloc2_1_0'
;------------------------------------------------------------
;_strcat.c:26: char * strcat (
;	-----------------------------------------
;	 function strcat
;	-----------------------------------------
_strcat:
;     genReceive
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, EXT(_strcat_dst_1_1), 0), stacked=0, isaddr=0
	sta	(_strcat_dst_1_1 + 1)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, EXT(_strcat_dst_1_1), 1), stacked=0, isaddr=0
	stx	_strcat_dst_1_1
;_strcat.c:33: while( *cp )
;     genAssign
;     loadRegFromAop (a, EXT(_strcat_dst_1_1), 0)
	lda	(_strcat_dst_1_1 + 1)
;     storeRegToAop (a, DIR(_strcat_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(_strcat_sloc0_1_0 + 1)
;     loadRegFromAop (a, EXT(_strcat_dst_1_1), 1)
	lda	_strcat_dst_1_1
;     storeRegToAop (a, DIR(_strcat_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*_strcat_sloc0_1_0
00101$:
;     genPointerGet
;     genFarPointerGet
;     loadRegFromAop (hx, DIR(_strcat_sloc0_1_0), 0)
	ldhx	*_strcat_sloc0_1_0
	lda	,x
;     storeRegToAop (a, DIR(_strcat_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*_strcat_sloc1_1_0
;     genIfx
	tst	*_strcat_sloc1_1_0
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00111$
00113$:
;_strcat.c:34: cp++;                   /* find end of dst */
; checking lic
; checking IS_ITEMP
; pset=0, pget=0
;     genPlus
; IS_AOP_HX = 0
;     loadRegFromAop (hx, DIR(_strcat_sloc0_1_0), 0)
	ldhx	*_strcat_sloc0_1_0
	aix	#1
;     storeRegToAop (hx, DIR(_strcat_sloc0_1_0), 0), stacked=0, isaddr=0
	sthx	*_strcat_sloc0_1_0
; Peephole 3	- shortened jmp to bra
	bra	00101$
;_strcat.c:36: while( *cp++ = *src++ ) ;       /* Copy src to end of dst */
00111$:
;     genAssign
;     loadRegFromAop (a, EXT(_strcat_PARM_2), 0)
	lda	(_strcat_PARM_2 + 1)
;     storeRegToAop (a, DIR(_strcat_sloc2_1_0), 0), stacked=0, isaddr=0
	sta	*(_strcat_sloc2_1_0 + 1)
;     loadRegFromAop (a, EXT(_strcat_PARM_2), 1)
	lda	_strcat_PARM_2
;     storeRegToAop (a, DIR(_strcat_sloc2_1_0), 1), stacked=0, isaddr=0
	sta	*_strcat_sloc2_1_0
;     genAssign
00104$:
;     genPointerGet
;     genFarPointerGet
;     loadRegFromAop (hx, DIR(_strcat_sloc2_1_0), 0)
	ldhx	*_strcat_sloc2_1_0
	lda	,x
	aix	#1
;     storeRegToAop (a, DIR(_strcat_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*_strcat_sloc1_1_0
;     storeRegToAop (hx, DIR(_strcat_sloc2_1_0), 0), stacked=0, isaddr=0
	sthx	*_strcat_sloc2_1_0
;     genPointerSet
;     genFarPointerSet
;     loadRegFromAop (hx, DIR(_strcat_sloc0_1_0), 0)
	ldhx	*_strcat_sloc0_1_0
;     loadRegFromAop (a, DIR(_strcat_sloc1_1_0), 0)
	lda	*_strcat_sloc1_1_0
	sta	,x
	aix	#1
;     storeRegToAop (hx, DIR(_strcat_sloc0_1_0), 0), stacked=0, isaddr=0
	sthx	*_strcat_sloc0_1_0
;     genIfx
	tst	*_strcat_sloc1_1_0
;     genIfxJump
; Peephole 2c	- eliminated jmp
	bne	00104$
00114$:
;_strcat.c:38: return( dst );                  /* return dst */
;     genRet
;     loadRegFromAop (x, EXT(_strcat_dst_1_1), 1)
	ldx	_strcat_dst_1_1
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(_strcat_dst_1_1), 0)
	lda	(_strcat_dst_1_1 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00107$:
	rts
	.area CSEG
	.area XINIT
