;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.4.0 Tue Oct 12 01:19:09 2004

;--------------------------------------------------------
	.module _strcmp
	.optsdcc -mmcs51 --model-large
	
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl _strcmp_PARM_2
	.globl _strcmp
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
;--------------------------------------------------------
; special function bits 
;--------------------------------------------------------
;--------------------------------------------------------
; overlayable register banks 
;--------------------------------------------------------
	.area REG_BANK_0	(REL,OVR,DATA)
	.ds 8
;--------------------------------------------------------
; internal ram data
;--------------------------------------------------------
	.area DSEG    (DATA)
;--------------------------------------------------------
; overlayable items in internal ram 
;--------------------------------------------------------
	.area	OSEG    (OVR,DATA)
_strcmp_sloc0_1_0::
	.ds 1
;--------------------------------------------------------
; indirectly addressable internal ram data
;--------------------------------------------------------
	.area ISEG    (DATA)
;--------------------------------------------------------
; bit data
;--------------------------------------------------------
	.area BSEG    (BIT)
;--------------------------------------------------------
; external ram data
;--------------------------------------------------------
	.area XSEG    (XDATA)
_strcmp_PARM_2::
	.ds 3
_strcmp_asrc_1_1::
	.ds 3
_strcmp_ret_1_1::
	.ds 2
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG   (XDATA)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area GSINIT  (CODE)
	.area GSFINAL (CODE)
	.area GSINIT  (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME    (CODE)
	.area CSEG    (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG    (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function 'strcmp'
;------------------------------------------------------------
;adst                      Allocated with name '_strcmp_PARM_2'
;asrc                      Allocated with name '_strcmp_asrc_1_1'
;ret                       Allocated with name '_strcmp_ret_1_1'
;sloc0                     Allocated with name '_strcmp_sloc0_1_0'
;------------------------------------------------------------
;_strcmp.c:29: int strcmp (
;	-----------------------------------------
;	 function strcmp
;	-----------------------------------------
_strcmp:
	ar2 = 0x02
	ar3 = 0x03
	ar4 = 0x04
	ar5 = 0x05
	ar6 = 0x06
	ar7 = 0x07
	ar0 = 0x00
	ar1 = 0x01
;     genReceive
	mov	r2,b
	mov	r3,dph
	mov	a,dpl
	mov	dptr,#_strcmp_asrc_1_1
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
	inc	dptr
	mov	a,r2
	movx	@dptr,a
;_strcmp.c:48: while( ! (ret = *asrc - *adst) && *adst)
;     genAssign
	mov	dptr,#_strcmp_asrc_1_1
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
	mov	r3,a
	inc	dptr
	movx	a,@dptr
	mov	r4,a
;     genAssign
	mov	dptr,#_strcmp_PARM_2
	movx	a,@dptr
	mov	r5,a
	inc	dptr
	movx	a,@dptr
	mov	r6,a
	inc	dptr
	movx	a,@dptr
	mov	r7,a
00102$:
;     genPointerGet
;     genGenPointerGet
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	lcall	__gptrget
;     genCast
;       Peephole 105    removed redundant mov
	mov     r0,a
	rlc	a
	subb	a,acc
	mov	r1,a
;     genPointerGet
;     genGenPointerGet
	mov	dpl,r5
	mov	dph,r6
	mov	b,r7
	lcall	__gptrget
	mov	_strcmp_sloc0_1_0,a
;     genIpush
	push	ar5
	push	ar6
	push	ar7
;     genCast
	mov	r5,_strcmp_sloc0_1_0
	mov	a,_strcmp_sloc0_1_0
	rlc	a
	subb	a,acc
	mov	r6,a
;     genMinus
	mov	a,r0
	clr	c
;       Peephole 236.l  used r5 instead of ar5
	subb    a,r5
	mov	r0,a
	mov	a,r1
;       Peephole 236.l  used r6 instead of ar6
	subb    a,r6
	mov	r1,a
;     genAssign
	mov	dptr,#_strcmp_ret_1_1
	mov	a,r0
	movx	@dptr,a
	inc	dptr
	mov	a,r1
	movx	@dptr,a
;     genIpop
	pop	ar7
	pop	ar6
	pop	ar5
;     genIfx
	mov	a,r0
	orl	a,r1
;     genIfxJump
;       Peephole 109    removed ljmp by inverse jump logic
	jnz     00104$
00117$:
;     genIfx
	mov	a,_strcmp_sloc0_1_0
;     genIfxJump
;       Peephole 110    removed ljmp by inverse jump logic
	jz      00104$
00118$:
;_strcmp.c:49: ++asrc, ++adst;
;     genPlus
;     genPlusIncr
	inc	r2
	cjne	r2,#0x00,00119$
	inc	r3
00119$:
;     genAssign
	mov	dptr,#_strcmp_asrc_1_1
	mov	a,r2
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
	inc	dptr
	mov	a,r4
	movx	@dptr,a
;     genPlus
;     genPlusIncr
	inc	r5
;       Peephole 112.b  changed ljmp to sjmp
;       Peephole 243    avoided branch to sjmp
	cjne    r5,#0x00,00102$
	inc     r6
00120$:
	sjmp    00102$      
00104$:
;_strcmp.c:51: if ( ret < 0 )
;     genAssign
	mov	dptr,#_strcmp_asrc_1_1
	mov	a,r2
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
	inc	dptr
	mov	a,r4
	movx	@dptr,a
;     genAssign
	mov	dptr,#_strcmp_ret_1_1
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
;     genCmpLt
;     genCmp
;       Peephole 105    removed redundant mov
	mov     r3,a
;     genIfxJump
;       Peephole 111    removed ljmp by inverse jump logic
	jnb     acc.7,00108$
00121$:
;_strcmp.c:52: ret = -1 ;
;     genAssign
	mov	dptr,#_strcmp_ret_1_1
;       Peephole 101    removed redundant mov
	mov     a,#0xFF
	movx    @dptr,a
	inc     dptr
	movx    @dptr,a
;       Peephole 112.b  changed ljmp to sjmp
	sjmp    00109$
00108$:
;_strcmp.c:53: else if ( ret > 0 )
;     genCmpGt
;     genCmp
	clr	c
;       Peephole 181    changed mov to clr
	clr     a
	subb	a,r2
;       Peephole 159    avoided xrl during execution
	mov  a,#(0x00 ^ 0x80)
	mov	b,r3
	xrl	b,#0x80
	subb	a,b
;     genIfxJump
;       Peephole 108    removed ljmp by inverse jump logic
	jnc     00109$
00122$:
;_strcmp.c:54: ret = 1 ;
;     genAssign
;       Peephole 230    replaced inefficient 16 bit constant
	mov     dptr,#_strcmp_ret_1_1
	mov     a,#0x01
	movx    @dptr,a
	inc     dptr
	clr     a
	movx    @dptr,a
	mov     dptr,#_strcmp_ret_1_1
00109$:
;_strcmp.c:56: return( ret );
;     genAssign
	mov	dptr,#_strcmp_ret_1_1
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
;     genRet
;       Peephole 235    loading dph directly from a(ccumulator), r3 not set
	mov     dpl,r2
	mov     dph,a
00110$:
	ret
	.area CSEG    (CODE)
	.area XINIT   (CODE)
