;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.4.0 Tue Oct 12 01:21:39 2004

;--------------------------------------------------------
	.module ceilf
	
	.area CSEG
	.area GSINIT
	.area GSFINAL
	.area XINIT
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl _ceilf
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area OSEG    (OVR)
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area GSINIT
	.area GSFINAL
	.area GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME
	.area CSEG
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG
;------------------------------------------------------------
;Allocation info for local variables in function 'ceilf'
;------------------------------------------------------------
;x                         Allocated to stack - offset 2
;r                         Allocated to stack - offset -4
;sloc0                     Allocated to stack - offset -8
;------------------------------------------------------------
;ceilf.c:23: float ceilf(float x) reentrant
;	-----------------------------------------
;	 function ceilf
;	-----------------------------------------
_ceilf:
	ais	#-8
;ceilf.c:26: r=x;
;     genAssign
;     loadRegFromAop (a, SOF(x), 0)
	lda	14,s
;     storeRegToAop (a, EXT(___fs2slong_PARM_1), 0), stacked=0, isaddr=1
	sta	(___fs2slong_PARM_1 + 3)
;     loadRegFromAop (a, SOF(x), 1)
	lda	13,s
;     storeRegToAop (a, EXT(___fs2slong_PARM_1), 1), stacked=0, isaddr=1
	sta	(___fs2slong_PARM_1 + 2)
;     loadRegFromAop (a, SOF(x), 2)
	lda	12,s
;     storeRegToAop (a, EXT(___fs2slong_PARM_1), 2), stacked=0, isaddr=1
	sta	(___fs2slong_PARM_1 + 1)
;     loadRegFromAop (a, SOF(x), 3)
	lda	11,s
;     storeRegToAop (a, EXT(___fs2slong_PARM_1), 3), stacked=0, isaddr=1
	sta	___fs2slong_PARM_1
;     genCall
	jsr	___fs2slong
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, SOF(iTemp1), 0), stacked=0, isaddr=0
	sta	8,s
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, SOF(iTemp1), 1), stacked=0, isaddr=0
	stx	7,s
;     loadRegFromAop (a, DIR(__ret2), 0)
	lda	*__ret2
;     storeRegToAop (a, SOF(iTemp1), 2), stacked=0, isaddr=0
	sta	6,s
;     loadRegFromAop (a, DIR(__ret3), 0)
	lda	*__ret3
;     storeRegToAop (a, SOF(iTemp1), 3), stacked=0, isaddr=0
	sta	5,s
;     genAssign
;ceilf.c:27: if (r<0)
;     genCmpLt
;     genCmp
;     loadRegFromAop (a, SOF(iTemp0), 3)
	lda	5,s
	rola
;     genIfxJump
; Peephole 2a	- eliminated jmp
	bcc	00102$
00110$:
;ceilf.c:28: return r;
;     genAssign
;     loadRegFromAop (a, SOF(iTemp0), 0)
	lda	8,s
;     storeRegToAop (a, EXT(___slong2fs_PARM_1), 0), stacked=0, isaddr=1
	sta	(___slong2fs_PARM_1 + 3)
;     loadRegFromAop (a, SOF(iTemp0), 1)
	lda	7,s
;     storeRegToAop (a, EXT(___slong2fs_PARM_1), 1), stacked=0, isaddr=1
	sta	(___slong2fs_PARM_1 + 2)
;     loadRegFromAop (a, SOF(iTemp0), 2)
	lda	6,s
;     storeRegToAop (a, EXT(___slong2fs_PARM_1), 2), stacked=0, isaddr=1
	sta	(___slong2fs_PARM_1 + 1)
;     loadRegFromAop (a, SOF(iTemp0), 3)
	lda	5,s
;     storeRegToAop (a, EXT(___slong2fs_PARM_1), 3), stacked=0, isaddr=1
	sta	___slong2fs_PARM_1
;     genCall
	jsr	___slong2fs
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, SOF(iTemp3), 0), stacked=0, isaddr=0
	sta	4,s
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, SOF(iTemp3), 1), stacked=0, isaddr=0
	stx	3,s
;     loadRegFromAop (a, DIR(__ret2), 0)
	lda	*__ret2
;     storeRegToAop (a, SOF(iTemp3), 2), stacked=0, isaddr=0
	sta	2,s
;     loadRegFromAop (a, DIR(__ret3), 0)
	lda	*__ret3
;     storeRegToAop (a, SOF(iTemp3), 3), stacked=0, isaddr=0
	sta	1,s
;     genRet
;     loadRegFromAop (a, SOF(iTemp3), 3)
	lda	1,s
;     storeRegToAop (a, DIR(__ret3), 0), stacked=0, isaddr=0
	sta	*__ret3
;     loadRegFromAop (a, SOF(iTemp3), 2)
	lda	2,s
;     storeRegToAop (a, DIR(__ret2), 0), stacked=0, isaddr=0
	sta	*__ret2
;     loadRegFromAop (x, SOF(iTemp3), 1)
	ldx	3,s
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, SOF(iTemp3), 0)
	lda	4,s
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
	jmp	00104$
00102$:
;ceilf.c:30: return (r+((r<x)?1:0));
;     genAssign
;     loadRegFromAop (a, SOF(iTemp0), 0)
	lda	8,s
;     storeRegToAop (a, EXT(___slong2fs_PARM_1), 0), stacked=0, isaddr=1
	sta	(___slong2fs_PARM_1 + 3)
;     loadRegFromAop (a, SOF(iTemp0), 1)
	lda	7,s
;     storeRegToAop (a, EXT(___slong2fs_PARM_1), 1), stacked=0, isaddr=1
	sta	(___slong2fs_PARM_1 + 2)
;     loadRegFromAop (a, SOF(iTemp0), 2)
	lda	6,s
;     storeRegToAop (a, EXT(___slong2fs_PARM_1), 2), stacked=0, isaddr=1
	sta	(___slong2fs_PARM_1 + 1)
;     loadRegFromAop (a, SOF(iTemp0), 3)
	lda	5,s
;     storeRegToAop (a, EXT(___slong2fs_PARM_1), 3), stacked=0, isaddr=1
	sta	___slong2fs_PARM_1
;     genCall
	jsr	___slong2fs
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, EXT(___fslt_PARM_1), 0), stacked=0, isaddr=1
	sta	(___fslt_PARM_1 + 3)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, EXT(___fslt_PARM_1), 1), stacked=0, isaddr=1
	stx	(___fslt_PARM_1 + 2)
;     loadRegFromAop (a, DIR(__ret2), 0)
	lda	*__ret2
;     storeRegToAop (a, EXT(___fslt_PARM_1), 2), stacked=0, isaddr=1
	sta	(___fslt_PARM_1 + 1)
;     loadRegFromAop (a, DIR(__ret3), 0)
	lda	*__ret3
;     storeRegToAop (a, EXT(___fslt_PARM_1), 3), stacked=0, isaddr=1
	sta	___fslt_PARM_1
;     genAssign
;     loadRegFromAop (a, SOF(x), 0)
	lda	14,s
;     storeRegToAop (a, EXT(___fslt_PARM_2), 0), stacked=0, isaddr=1
	sta	(___fslt_PARM_2 + 3)
;     loadRegFromAop (a, SOF(x), 1)
	lda	13,s
;     storeRegToAop (a, EXT(___fslt_PARM_2), 1), stacked=0, isaddr=1
	sta	(___fslt_PARM_2 + 2)
;     loadRegFromAop (a, SOF(x), 2)
	lda	12,s
;     storeRegToAop (a, EXT(___fslt_PARM_2), 2), stacked=0, isaddr=1
	sta	(___fslt_PARM_2 + 1)
;     loadRegFromAop (a, SOF(x), 3)
	lda	11,s
;     storeRegToAop (a, EXT(___fslt_PARM_2), 3), stacked=0, isaddr=1
	sta	___fslt_PARM_2
;     genCall
	jsr	___fslt
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     genIfx
	tsta
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00106$
00111$:
; forgot to free a
;     genAssign
;     loadRegFromAop (a, LIT(#0x01), 0)
	lda	#0x01
;     storeRegToAop (a, SOF(iTemp6), 0), stacked=0, isaddr=0
	sta	1,s
; Peephole 3	- shortened jmp to bra
	bra	00107$
00106$:
;     genAssign
;     loadRegFromAop (a, LIT(#0x00), 0)
	lda	#0x00
;     storeRegToAop (a, SOF(iTemp6), 0), stacked=0, isaddr=0
	sta	1,s
00107$:
;     genCast
;     loadRegFromAop (a, SOF(iTemp6), 0)
	lda	1,s
;     storeRegToAop (a, SOF(iTemp7), 0), stacked=0, isaddr=0
	sta	2,s
	clra
;     storeRegToAop (a, SOF(iTemp7), 1), stacked=0, isaddr=0
	sta	1,s
;     genCast
;     loadRegFromAop (a, SOF(iTemp7), 0)
	lda	2,s
;     storeRegToAop (a, SOF(iTemp8), 0), stacked=0, isaddr=0
	sta	4,s
;     loadRegFromAop (a, SOF(iTemp7), 1)
	lda	1,s
;     storeRegToAop (a, SOF(iTemp8), 1), stacked=0, isaddr=0
	sta	3,s
;     loadRegFromAop (a, SOF(iTemp7), 1)
	lda	1,s
	rola	
	clra	
	sbc	#0x00
;     storeRegToAop (a, SOF(iTemp8), 2), stacked=0, isaddr=0
	sta	2,s
;     storeRegToAop (a, SOF(iTemp8), 3), stacked=0, isaddr=0
	sta	1,s
; checking lic
; checking IS_ITEMP
;     genPlus
;  left size = 4
;  right size = 4
;  result size = 4
;     loadRegFromAop (a, SOF(iTemp0), 0)
	lda	8,s
	add	4,s
;     storeRegToAop (a, EXT(___slong2fs_PARM_1), 0), stacked=0, isaddr=1
	sta	(___slong2fs_PARM_1 + 3)
;     loadRegFromAop (a, SOF(iTemp0), 1)
	lda	7,s
	adc	3,s
;     storeRegToAop (a, EXT(___slong2fs_PARM_1), 1), stacked=0, isaddr=1
	sta	(___slong2fs_PARM_1 + 2)
;     loadRegFromAop (a, SOF(iTemp0), 2)
	lda	6,s
	adc	2,s
;     storeRegToAop (a, EXT(___slong2fs_PARM_1), 2), stacked=0, isaddr=1
	sta	(___slong2fs_PARM_1 + 1)
;     loadRegFromAop (a, SOF(iTemp0), 3)
	lda	5,s
	adc	1,s
;     storeRegToAop (a, EXT(___slong2fs_PARM_1), 3), stacked=0, isaddr=1
	sta	___slong2fs_PARM_1
;     genCall
	jsr	___slong2fs
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, SOF(iTemp10), 0), stacked=0, isaddr=0
	sta	4,s
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, SOF(iTemp10), 1), stacked=0, isaddr=0
	stx	3,s
;     loadRegFromAop (a, DIR(__ret2), 0)
	lda	*__ret2
;     storeRegToAop (a, SOF(iTemp10), 2), stacked=0, isaddr=0
	sta	2,s
;     loadRegFromAop (a, DIR(__ret3), 0)
	lda	*__ret3
;     storeRegToAop (a, SOF(iTemp10), 3), stacked=0, isaddr=0
	sta	1,s
;     genRet
;     loadRegFromAop (a, SOF(iTemp10), 3)
	lda	1,s
;     storeRegToAop (a, DIR(__ret3), 0), stacked=0, isaddr=0
	sta	*__ret3
;     loadRegFromAop (a, SOF(iTemp10), 2)
	lda	2,s
;     storeRegToAop (a, DIR(__ret2), 0), stacked=0, isaddr=0
	sta	*__ret2
;     loadRegFromAop (x, SOF(iTemp10), 1)
	ldx	3,s
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, SOF(iTemp10), 0)
	lda	4,s
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00104$:
	ais	#8
	rts
	.area CSEG
	.area XINIT
