;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.4.0 Tue Oct 12 01:21:28 2004

;--------------------------------------------------------
	.module _modulong
	
	.area CSEG
	.area GSINIT
	.area GSFINAL
	.area XINIT
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl __modulong_PARM_2
	.globl __modulong_PARM_1
	.globl __modulong
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area	OSEG    (OVR)
__modulong_sloc0_1_0::
	.ds 1
__modulong_sloc1_1_0::
	.ds 1
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
__modulong_PARM_1::
	.ds 4
__modulong_PARM_2::
	.ds 4
__modulong_count_1_1::
	.ds 1
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area GSINIT
	.area GSFINAL
	.area GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME
	.area CSEG
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG
;------------------------------------------------------------
;Allocation info for local variables in function '_modulong'
;------------------------------------------------------------
;a                         Allocated with name '__modulong_PARM_1'
;b                         Allocated with name '__modulong_PARM_2'
;count                     Allocated with name '__modulong_count_1_1'
;sloc0                     Allocated with name '__modulong_sloc0_1_0'
;sloc1                     Allocated with name '__modulong_sloc1_1_0'
;------------------------------------------------------------
;_modulong.c:340: _modulong (unsigned long a, unsigned long b)
;	-----------------------------------------
;	 function _modulong
;	-----------------------------------------
__modulong:
;_modulong.c:342: unsigned char count = 0;
;     genAssign
;     loadRegFromAop (a, LIT(#0x00), 0)
	lda	#0x00
;     storeRegToAop (a, EXT(__modulong_count_1_1), 0), stacked=0, isaddr=0
	sta	__modulong_count_1_1
;_modulong.c:344: while (!MSB_SET(b))
;     genAssign
	mov	#0x00,*__modulong_sloc0_1_0
00103$:
;     genGetHbit
;     loadRegFromAop (a, EXT(__modulong_PARM_2), 3)
	lda	__modulong_PARM_2
	rola
	clra
	rola
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     genIfx
	tsta
;     genIfxJump
; Peephole 2c	- eliminated jmp
	bne	00117$
00119$:
; forgot to free a
;_modulong.c:346: b <<= 1;
;     genLeftShift
;     genLeftShiftLiteral
;     genlshFour
;     loadRegFromAop (xa, EXT(__modulong_PARM_2), 0)
;     loadRegFromAop (a, EXT(__modulong_PARM_2), 0)
	lda	(__modulong_PARM_2 + 3)
;     loadRegFromAop (x, EXT(__modulong_PARM_2), 1)
	ldx	(__modulong_PARM_2 + 2)
	lsla
	rolx
;     storeRegToAop (xa, EXT(__modulong_PARM_2), 0), stacked=0, isaddr=1
;     storeRegToAop (a, EXT(__modulong_PARM_2), 0), stacked=0, isaddr=1
	sta	(__modulong_PARM_2 + 3)
;     storeRegToAop (x, EXT(__modulong_PARM_2), 1), stacked=0, isaddr=1
	stx	(__modulong_PARM_2 + 2)
;     loadRegFromAop (xa, EXT(__modulong_PARM_2), 2)
;     loadRegFromAop (a, EXT(__modulong_PARM_2), 2)
	lda	(__modulong_PARM_2 + 1)
;     loadRegFromAop (x, EXT(__modulong_PARM_2), 3)
	ldx	__modulong_PARM_2
	rola
	rolx
;     storeRegToAop (xa, EXT(__modulong_PARM_2), 2), stacked=0, isaddr=1
;     storeRegToAop (a, EXT(__modulong_PARM_2), 2), stacked=0, isaddr=1
	sta	(__modulong_PARM_2 + 1)
;     storeRegToAop (x, EXT(__modulong_PARM_2), 3), stacked=0, isaddr=1
	stx	__modulong_PARM_2
;_modulong.c:347: if (b > a)
;     genCmpGt
;     genCmp
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 0)
	lda	(__modulong_PARM_1 + 3)
	sub	(__modulong_PARM_2 + 3)
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 1)
	lda	(__modulong_PARM_1 + 2)
	sbc	(__modulong_PARM_2 + 2)
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 2)
	lda	(__modulong_PARM_1 + 1)
	sbc	(__modulong_PARM_2 + 1)
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 3)
	lda	__modulong_PARM_1
	sbc	__modulong_PARM_2
;     genIfxJump
; Peephole 2a	- eliminated jmp
	bcc	00102$
00120$:
;_modulong.c:349: b >>=1;
;     genRightShift
;     genRightShiftLiteral
;     genrshFour
;     loadRegFromAop (xa, EXT(__modulong_PARM_2), 2)
;     loadRegFromAop (a, EXT(__modulong_PARM_2), 2)
	lda	(__modulong_PARM_2 + 1)
;     loadRegFromAop (x, EXT(__modulong_PARM_2), 3)
	ldx	__modulong_PARM_2
	lsrx
	rola
;     storeRegToAop (xa, EXT(__modulong_PARM_2), 2), stacked=0, isaddr=1
;     storeRegToAop (a, EXT(__modulong_PARM_2), 2), stacked=0, isaddr=1
	sta	(__modulong_PARM_2 + 1)
;     storeRegToAop (x, EXT(__modulong_PARM_2), 3), stacked=0, isaddr=1
	stx	__modulong_PARM_2
;     loadRegFromAop (xa, EXT(__modulong_PARM_2), 0)
;     loadRegFromAop (a, EXT(__modulong_PARM_2), 0)
	lda	(__modulong_PARM_2 + 3)
;     loadRegFromAop (x, EXT(__modulong_PARM_2), 1)
	ldx	(__modulong_PARM_2 + 2)
	rorx
	rora
;     storeRegToAop (xa, EXT(__modulong_PARM_2), 0), stacked=0, isaddr=1
;     storeRegToAop (a, EXT(__modulong_PARM_2), 0), stacked=0, isaddr=1
	sta	(__modulong_PARM_2 + 3)
;     storeRegToAop (x, EXT(__modulong_PARM_2), 1), stacked=0, isaddr=1
	stx	(__modulong_PARM_2 + 2)
;_modulong.c:350: break;
; Peephole 3	- shortened jmp to bra
	bra	00117$
00102$:
;_modulong.c:352: count++;
; checking lic
; checking IS_ITEMP
; pset=0, pget=0
;     genPlus
; IS_AOP_HX = 0
; icount = 1, sameRegs=1
;     genPlusIncr
	inc	*__modulong_sloc0_1_0
;     genAssign
;     loadRegFromAop (a, DIR(__modulong_sloc0_1_0), 0)
	lda	*__modulong_sloc0_1_0
;     storeRegToAop (a, EXT(__modulong_count_1_1), 0), stacked=0, isaddr=0
	sta	__modulong_count_1_1
	jmp	00103$
;_modulong.c:354: do
00117$:
;     genAssign
;     loadRegFromAop (a, EXT(__modulong_count_1_1), 0)
	lda	__modulong_count_1_1
;     storeRegToAop (a, DIR(__modulong_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*__modulong_sloc0_1_0
00108$:
;_modulong.c:356: if (a >= b)
;     genCmpLt
;     genCmp
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 0)
	lda	(__modulong_PARM_1 + 3)
	sub	(__modulong_PARM_2 + 3)
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 1)
	lda	(__modulong_PARM_1 + 2)
	sbc	(__modulong_PARM_2 + 2)
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 2)
	lda	(__modulong_PARM_1 + 1)
	sbc	(__modulong_PARM_2 + 1)
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 3)
	lda	__modulong_PARM_1
	sbc	__modulong_PARM_2
;     genIfxJump
; Peephole 2b	- eliminated jmp
	bcs	00107$
00121$:
;_modulong.c:357: a -= b;
;     genMinus
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 0)
	lda	(__modulong_PARM_1 + 3)
	sub	(__modulong_PARM_2 + 3)
;     storeRegToAop (a, EXT(__modulong_PARM_1), 0), stacked=0, isaddr=1
	sta	(__modulong_PARM_1 + 3)
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 1)
	lda	(__modulong_PARM_1 + 2)
	sbc	(__modulong_PARM_2 + 2)
;     storeRegToAop (a, EXT(__modulong_PARM_1), 1), stacked=0, isaddr=1
	sta	(__modulong_PARM_1 + 2)
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 2)
	lda	(__modulong_PARM_1 + 1)
	sbc	(__modulong_PARM_2 + 1)
;     storeRegToAop (a, EXT(__modulong_PARM_1), 2), stacked=0, isaddr=1
	sta	(__modulong_PARM_1 + 1)
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 3)
	lda	__modulong_PARM_1
	sbc	__modulong_PARM_2
;     storeRegToAop (a, EXT(__modulong_PARM_1), 3), stacked=0, isaddr=1
	sta	__modulong_PARM_1
00107$:
;_modulong.c:358: b >>= 1;
;     genRightShift
;     genRightShiftLiteral
;     genrshFour
;     loadRegFromAop (xa, EXT(__modulong_PARM_2), 2)
;     loadRegFromAop (a, EXT(__modulong_PARM_2), 2)
	lda	(__modulong_PARM_2 + 1)
;     loadRegFromAop (x, EXT(__modulong_PARM_2), 3)
	ldx	__modulong_PARM_2
	lsrx
	rola
;     storeRegToAop (xa, EXT(__modulong_PARM_2), 2), stacked=0, isaddr=1
;     storeRegToAop (a, EXT(__modulong_PARM_2), 2), stacked=0, isaddr=1
	sta	(__modulong_PARM_2 + 1)
;     storeRegToAop (x, EXT(__modulong_PARM_2), 3), stacked=0, isaddr=1
	stx	__modulong_PARM_2
;     loadRegFromAop (xa, EXT(__modulong_PARM_2), 0)
;     loadRegFromAop (a, EXT(__modulong_PARM_2), 0)
	lda	(__modulong_PARM_2 + 3)
;     loadRegFromAop (x, EXT(__modulong_PARM_2), 1)
	ldx	(__modulong_PARM_2 + 2)
	rorx
	rora
;     storeRegToAop (xa, EXT(__modulong_PARM_2), 0), stacked=0, isaddr=1
;     storeRegToAop (a, EXT(__modulong_PARM_2), 0), stacked=0, isaddr=1
	sta	(__modulong_PARM_2 + 3)
;     storeRegToAop (x, EXT(__modulong_PARM_2), 1), stacked=0, isaddr=1
	stx	(__modulong_PARM_2 + 2)
;_modulong.c:360: while (count--);
;     genAssign
	mov	*__modulong_sloc0_1_0,*__modulong_sloc1_1_0
;     genMinus
;     genMinusDec
	dec	*__modulong_sloc0_1_0
;     genIfx
	tst	*__modulong_sloc1_1_0
;     genIfxJump
; Peephole 2c	- eliminated jmp
	bne	00108$
00122$:
;_modulong.c:362: return a;
;     genRet
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 3)
	lda	__modulong_PARM_1
;     storeRegToAop (a, DIR(__ret3), 0), stacked=0, isaddr=0
	sta	*__ret3
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 2)
	lda	(__modulong_PARM_1 + 1)
;     storeRegToAop (a, DIR(__ret2), 0), stacked=0, isaddr=0
	sta	*__ret2
;     loadRegFromAop (x, EXT(__modulong_PARM_1), 1)
	ldx	(__modulong_PARM_1 + 2)
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(__modulong_PARM_1), 0)
	lda	(__modulong_PARM_1 + 3)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00111$:
	rts
	.area CSEG
	.area XINIT
