;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.4.0 Tue Oct 12 01:21:29 2004

;--------------------------------------------------------
	.module _strcspn
	
	.area CSEG
	.area GSINIT
	.area GSFINAL
	.area XINIT
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl _strcspn_PARM_2
	.globl _strcspn
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
_strcspn_sloc0_1_0::
	.ds 2
_strcspn_sloc1_1_0::
	.ds 1
_strcspn_sloc2_1_0::
	.ds 2
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area OSEG    (OVR)
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
_strcspn_PARM_2::
	.ds 2
_strcspn_string_1_1::
	.ds 2
_strcspn_ch_1_1::
	.ds 1
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area GSINIT
	.area GSFINAL
	.area GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME
	.area CSEG
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG
;------------------------------------------------------------
;Allocation info for local variables in function 'strcspn'
;------------------------------------------------------------
;sloc0                     Allocated with name '_strcspn_sloc0_1_0'
;sloc1                     Allocated with name '_strcspn_sloc1_1_0'
;sloc2                     Allocated with name '_strcspn_sloc2_1_0'
;control                   Allocated with name '_strcspn_PARM_2'
;string                    Allocated with name '_strcspn_string_1_1'
;count                     Allocated to registers 
;ch                        Allocated with name '_strcspn_ch_1_1'
;------------------------------------------------------------
;_strcspn.c:26: int strcspn ( 
;	-----------------------------------------
;	 function strcspn
;	-----------------------------------------
_strcspn:
;     genReceive
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, EXT(_strcspn_string_1_1), 0), stacked=0, isaddr=0
	sta	(_strcspn_string_1_1 + 1)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, EXT(_strcspn_string_1_1), 1), stacked=0, isaddr=0
	stx	_strcspn_string_1_1
;_strcspn.c:34: while (ch = *string) {
;     genAssign
	mov	#0x00,*(_strcspn_sloc0_1_0 + 1)
	mov	#0x00,*_strcspn_sloc0_1_0
00104$:
;     genPointerGet
;     genFarPointerGet
;     loadRegFromAop (hx, EXT(_strcspn_string_1_1), 0)
;     loadRegFromAop (a, EXT(_strcspn_string_1_1), 1)
	lda	_strcspn_string_1_1
;     loadRegFromAop (x, EXT(_strcspn_string_1_1), 0)
	ldx	(_strcspn_string_1_1 + 1)
; transferRegReg(a,h)
	psha
	pulh
	lda	,x
;     storeRegToAop (a, DIR(_strcspn_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*_strcspn_sloc1_1_0
;     genAssign
;     loadRegFromAop (a, DIR(_strcspn_sloc1_1_0), 0)
	lda	*_strcspn_sloc1_1_0
;     storeRegToAop (a, EXT(_strcspn_ch_1_1), 0), stacked=0, isaddr=0
	sta	_strcspn_ch_1_1
;     genIfx
	tst	*_strcspn_sloc1_1_0
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00106$
00112$:
;_strcspn.c:35: if (strchr(control,ch))
;     genAssign
;     loadRegFromAop (a, EXT(_strcspn_ch_1_1), 0)
	lda	_strcspn_ch_1_1
;     storeRegToAop (a, EXT(_strchr_PARM_2), 0), stacked=0, isaddr=1
	sta	_strchr_PARM_2
;     genCall
;     loadRegFromAop (x, EXT(_strcspn_PARM_2), 1)
	ldx	_strcspn_PARM_2
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(_strcspn_PARM_2), 0)
	lda	(_strcspn_PARM_2 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
	jsr	_strchr
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, DIR(_strcspn_sloc2_1_0), 0), stacked=0, isaddr=0
	sta	*(_strcspn_sloc2_1_0 + 1)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, DIR(_strcspn_sloc2_1_0), 1), stacked=0, isaddr=0
	stx	*_strcspn_sloc2_1_0
;     genIfx
;     loadRegFromAop (a, DIR(_strcspn_sloc2_1_0), 0)
	lda	*(_strcspn_sloc2_1_0 + 1)
	ora	*_strcspn_sloc2_1_0
;     genIfxJump
; Peephole 2c	- eliminated jmp
	bne	00106$
00113$:
;_strcspn.c:38: count++ ;
; checking lic
; checking IS_ITEMP
; pset=0, pget=0
;     genPlus
; IS_AOP_HX = 0
;     loadRegFromAop (hx, DIR(_strcspn_sloc0_1_0), 0)
	ldhx	*_strcspn_sloc0_1_0
	aix	#1
;     storeRegToAop (hx, DIR(_strcspn_sloc0_1_0), 0), stacked=0, isaddr=0
	sthx	*_strcspn_sloc0_1_0
; Peephole 3	- shortened jmp to bra
	bra	00104$
00106$:
;_strcspn.c:41: return count ;
;     genRet
;     loadRegFromAop (x, DIR(_strcspn_sloc0_1_0), 1)
	ldx	*_strcspn_sloc0_1_0
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, DIR(_strcspn_sloc0_1_0), 0)
	lda	*(_strcspn_sloc0_1_0 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00107$:
	rts
	.area CSEG
	.area XINIT
