;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.4.0 Tue Oct 12 01:18:14 2004

;--------------------------------------------------------
	.module _fsmul
	.optsdcc -mmcs51 --model-small
	
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl ___fsmul_PARM_2
	.globl ___fsmul
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
;--------------------------------------------------------
; special function bits 
;--------------------------------------------------------
;--------------------------------------------------------
; overlayable register banks 
;--------------------------------------------------------
	.area REG_BANK_0	(REL,OVR,DATA)
	.ds 8
;--------------------------------------------------------
; internal ram data
;--------------------------------------------------------
	.area DSEG    (DATA)
___fsmul_PARM_2::
	.ds 4
___fsmul_fl1_1_1::
	.ds 4
___fsmul_fl2_1_1::
	.ds 4
___fsmul_result_1_1::
	.ds 4
___fsmul_exp_1_1::
	.ds 2
___fsmul_sign_1_1::
	.ds 1
;--------------------------------------------------------
; overlayable items in internal ram 
;--------------------------------------------------------
	.area OSEG    (OVR,DATA)
;--------------------------------------------------------
; indirectly addressable internal ram data
;--------------------------------------------------------
	.area ISEG    (DATA)
;--------------------------------------------------------
; bit data
;--------------------------------------------------------
	.area BSEG    (BIT)
;--------------------------------------------------------
; external ram data
;--------------------------------------------------------
	.area XSEG    (XDATA)
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG   (XDATA)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area GSINIT  (CODE)
	.area GSFINAL (CODE)
	.area GSINIT  (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME    (CODE)
	.area CSEG    (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG    (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function '__fsmul'
;------------------------------------------------------------
;a2                        Allocated with name '___fsmul_PARM_2'
;a1                        Allocated to registers r2 r3 r4 r5 
;fl1                       Allocated with name '___fsmul_fl1_1_1'
;fl2                       Allocated with name '___fsmul_fl2_1_1'
;result                    Allocated with name '___fsmul_result_1_1'
;exp                       Allocated with name '___fsmul_exp_1_1'
;sign                      Allocated with name '___fsmul_sign_1_1'
;------------------------------------------------------------
;_fsmul.c:28: float __fsmul (float a1, float a2) {
;	-----------------------------------------
;	 function __fsmul
;	-----------------------------------------
___fsmul:
	ar2 = 0x02
	ar3 = 0x03
	ar4 = 0x04
	ar5 = 0x05
	ar6 = 0x06
	ar7 = 0x07
	ar0 = 0x00
	ar1 = 0x01
;     genReceive
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	mov	r5,a
;_fsmul.c:34: fl1.f = a1;
;     genPointerSet
;     genNearPointerSet
;     genDataPointerSet
	mov	___fsmul_fl1_1_1,r2
	mov	(___fsmul_fl1_1_1 + 1),r3
	mov	(___fsmul_fl1_1_1 + 2),r4
	mov	(___fsmul_fl1_1_1 + 3),r5
;_fsmul.c:35: fl2.f = a2;
;     genPointerSet
;     genNearPointerSet
;     genDataPointerSet
	mov	___fsmul_fl2_1_1,___fsmul_PARM_2
	mov	(___fsmul_fl2_1_1 + 1),(___fsmul_PARM_2 + 1)
	mov	(___fsmul_fl2_1_1 + 2),(___fsmul_PARM_2 + 2)
	mov	(___fsmul_fl2_1_1 + 3),(___fsmul_PARM_2 + 3)
;_fsmul.c:37: if (!fl1.l || !fl2.l)
;     genAssign
;     genIfx
	mov	a,___fsmul_fl1_1_1
	orl	a,(___fsmul_fl1_1_1 + 1)
	orl	a,(___fsmul_fl1_1_1 + 2)
	orl	a,(___fsmul_fl1_1_1 + 3)
;     genIfxJump
;       Peephole 110    removed ljmp by inverse jump logic
	jz      00101$
00114$:
;     genAssign
;     genIfx
	mov	a,___fsmul_fl2_1_1
	orl	a,(___fsmul_fl2_1_1 + 1)
	orl	a,(___fsmul_fl2_1_1 + 2)
	orl	a,(___fsmul_fl2_1_1 + 3)
;     genIfxJump
;       Peephole 109    removed ljmp by inverse jump logic
	jnz     00102$
00115$:
00101$:
;_fsmul.c:38: return (0);
;     genRet
	mov	dpl,#0x00
;       Peephole 3.a    changed mov to clr
;       Peephole 3.b    changed mov to clr
	clr     a
	mov     dph,a
	mov     b,a
;       Peephole 251    replaced ljmp to ret with ret
	ret
00102$:
;_fsmul.c:41: sign = SIGN (fl1.l) ^ SIGN (fl2.l);
;     genAssign
;     genGetHbit
	mov	a,(___fsmul_fl1_1_1 + 3)
	rl	a
	anl	a,#0x01
	mov	r2,a
;     genAssign
;     genGetHbit
	mov	a,(___fsmul_fl2_1_1 + 3)
	rl	a
	anl	a,#0x01
;     genXor
;       Peephole 105    removed redundant mov
	mov     r3,a
;       Peephole 236.n  used r2 instead of ar2
	xrl     a,r2
	mov	___fsmul_sign_1_1,a
;_fsmul.c:42: exp = EXP (fl1.l) - EXCESS;
;     genAssign
;     genRightShift
;     genRightShiftLiteral
;     genrshFour
	mov	r3,(___fsmul_fl1_1_1 + 2)
	mov	a,(___fsmul_fl1_1_1 + 3)
	mov	c,acc.7
	xch	a,r3
	rlc	a
	xch	a,r3
	rlc	a
	xch	a,r3
	anl	a,#0x01
	mov	r4,a
	mov	r5,#0x00
	mov	r6,#0x00
;     genAnd
	mov	r4,#0x00
;     genMinus
;       Peephole 3.c    changed mov to clr
	clr     a
	mov     r5,a
	mov     r6,a
	mov     a,r3
	add	a,#0x82
	mov	r3,a
	mov	a,r4
	addc	a,#0xff
	mov	r4,a
	mov	a,r5
	addc	a,#0xff
	mov	r5,a
	mov	a,r6
	addc	a,#0xff
	mov	r6,a
;     genCast
	mov	___fsmul_exp_1_1,r3
	mov	(___fsmul_exp_1_1 + 1),r4
;_fsmul.c:43: exp += EXP (fl2.l);
;     genAssign
;     genRightShift
;     genRightShiftLiteral
;     genrshFour
	mov	r3,(___fsmul_fl2_1_1 + 2)
	mov	a,(___fsmul_fl2_1_1 + 3)
	mov	c,acc.7
	xch	a,r3
	rlc	a
	xch	a,r3
	rlc	a
	xch	a,r3
	anl	a,#0x01
	mov	r4,a
	mov	r5,#0x00
	mov	r6,#0x00
;     genAnd
	mov	r4,#0x00
	mov	r5,#0x00
	mov	r6,#0x00
;     genCast
	mov	r7,___fsmul_exp_1_1
	mov	r0,(___fsmul_exp_1_1 + 1)
	mov	a,(___fsmul_exp_1_1 + 1)
	rlc	a
	subb	a,acc
	mov	r1,a
	mov	r2,a
;     genPlus
;       Peephole 236.g  used r3 instead of ar3
	mov     a,r3
;       Peephole 236.a  used r7 instead of ar7
	add     a,r7
	mov	r3,a
;       Peephole 236.g  used r4 instead of ar4
	mov     a,r4
;       Peephole 236.b  used r0 instead of ar0
	addc    a,r0
	mov	r4,a
;       Peephole 236.g  used r5 instead of ar5
	mov     a,r5
;       Peephole 236.b  used r1 instead of ar1
	addc    a,r1
	mov	r5,a
;       Peephole 236.g  used r6 instead of ar6
	mov     a,r6
;       Peephole 236.b  used r2 instead of ar2
	addc    a,r2
	mov	r6,a
;     genCast
	mov	___fsmul_exp_1_1,r3
	mov	(___fsmul_exp_1_1 + 1),r4
;_fsmul.c:45: fl1.l = MANT (fl1.l);
;     genAssign
;     genAnd
	mov	r2,___fsmul_fl1_1_1
	mov	r3,(___fsmul_fl1_1_1 + 1)
	mov	a,#0x7F
	anl	a,(___fsmul_fl1_1_1 + 2)
	mov	r4,a
	mov	r5,#0x00
;     genOr
	orl	ar4,#0x80
;     genPointerSet
;     genNearPointerSet
;     genDataPointerSet
	mov	___fsmul_fl1_1_1,r2
	mov	(___fsmul_fl1_1_1 + 1),r3
	mov	(___fsmul_fl1_1_1 + 2),r4
	mov	(___fsmul_fl1_1_1 + 3),r5
;_fsmul.c:46: fl2.l = MANT (fl2.l);
;     genAssign
;     genAnd
	mov	r2,___fsmul_fl2_1_1
	mov	r3,(___fsmul_fl2_1_1 + 1)
	mov	a,#0x7F
	anl	a,(___fsmul_fl2_1_1 + 2)
	mov	r4,a
	mov	r5,#0x00
;     genOr
	orl	ar4,#0x80
;     genPointerSet
;     genNearPointerSet
;     genDataPointerSet
	mov	___fsmul_fl2_1_1,r2
	mov	(___fsmul_fl2_1_1 + 1),r3
	mov	(___fsmul_fl2_1_1 + 2),r4
	mov	(___fsmul_fl2_1_1 + 3),r5
;_fsmul.c:49: result = (fl1.l >> 8) * (fl2.l >> 8);
;     genAssign
;     genRightShift
;     genRightShiftLiteral
;     genrshFour
	mov	r2,(___fsmul_fl1_1_1 + 1)
	mov	r3,(___fsmul_fl1_1_1 + 2)
	mov	r4,(___fsmul_fl1_1_1 + 3)
	mov	r5,#0x00
;     genAssign
;     genRightShift
;     genRightShiftLiteral
;     genrshFour
	mov	__mullong_PARM_2,(___fsmul_fl2_1_1 + 1)
	mov	(__mullong_PARM_2 + 1),(___fsmul_fl2_1_1 + 2)
	mov	(__mullong_PARM_2 + 2),(___fsmul_fl2_1_1 + 3)
	mov	(__mullong_PARM_2 + 3),#0x00
;     genCall
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	mov	a,r5
	lcall	__mullong
	mov	___fsmul_result_1_1,dpl
	mov	(___fsmul_result_1_1 + 1),dph
	mov	(___fsmul_result_1_1 + 2),b
	mov	(___fsmul_result_1_1 + 3),a
;_fsmul.c:50: result += ((fl1.l & (unsigned long) 0xFF) * (fl2.l >> 8)) >> 8;
;     genAssign
;     genAnd
	mov	r2,___fsmul_fl1_1_1
	mov	r3,#0x00
	mov	r4,#0x00
	mov	r5,#0x00
;     genAssign
;     genRightShift
;     genRightShiftLiteral
;     genrshFour
	mov	__mullong_PARM_2,(___fsmul_fl2_1_1 + 1)
	mov	(__mullong_PARM_2 + 1),(___fsmul_fl2_1_1 + 2)
	mov	(__mullong_PARM_2 + 2),(___fsmul_fl2_1_1 + 3)
	mov	(__mullong_PARM_2 + 3),#0x00
;     genCall
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	mov	a,r5
	lcall	__mullong
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	mov	r5,a
;     genRightShift
;     genRightShiftLiteral
;     genrshFour
	mov	ar2,r3
	mov	ar3,r4
	mov	ar4,r5
	mov	r5,#0x00
;     genPlus
;       Peephole 236.g  used r2 instead of ar2
	mov     a,r2
	add	a,___fsmul_result_1_1
	mov	___fsmul_result_1_1,a
;       Peephole 236.g  used r3 instead of ar3
	mov     a,r3
	addc	a,(___fsmul_result_1_1 + 1)
	mov	(___fsmul_result_1_1 + 1),a
;       Peephole 236.g  used r4 instead of ar4
	mov     a,r4
	addc	a,(___fsmul_result_1_1 + 2)
	mov	(___fsmul_result_1_1 + 2),a
;       Peephole 236.g  used r5 instead of ar5
	mov     a,r5
	addc	a,(___fsmul_result_1_1 + 3)
	mov	(___fsmul_result_1_1 + 3),a
;_fsmul.c:51: result += ((fl2.l & (unsigned long) 0xFF) * (fl1.l >> 8)) >> 8;
;     genAssign
;     genAnd
	mov	r2,___fsmul_fl2_1_1
	mov	r3,#0x00
	mov	r4,#0x00
	mov	r5,#0x00
;     genAssign
;     genRightShift
;     genRightShiftLiteral
;     genrshFour
	mov	__mullong_PARM_2,(___fsmul_fl1_1_1 + 1)
	mov	(__mullong_PARM_2 + 1),(___fsmul_fl1_1_1 + 2)
	mov	(__mullong_PARM_2 + 2),(___fsmul_fl1_1_1 + 3)
	mov	(__mullong_PARM_2 + 3),#0x00
;     genCall
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	mov	a,r5
	lcall	__mullong
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	mov	r5,a
;     genRightShift
;     genRightShiftLiteral
;     genrshFour
	mov	ar2,r3
	mov	ar3,r4
	mov	ar4,r5
	mov	r5,#0x00
;     genPlus
;       Peephole 236.g  used r2 instead of ar2
	mov     a,r2
	add	a,___fsmul_result_1_1
	mov	___fsmul_result_1_1,a
;       Peephole 236.g  used r3 instead of ar3
	mov     a,r3
	addc	a,(___fsmul_result_1_1 + 1)
	mov	(___fsmul_result_1_1 + 1),a
;       Peephole 236.g  used r4 instead of ar4
	mov     a,r4
	addc	a,(___fsmul_result_1_1 + 2)
	mov	(___fsmul_result_1_1 + 2),a
;       Peephole 236.g  used r5 instead of ar5
	mov     a,r5
	addc	a,(___fsmul_result_1_1 + 3)
	mov	(___fsmul_result_1_1 + 3),a
;_fsmul.c:53: if (result & SIGNBIT)
;     genAnd
	mov	a,(___fsmul_result_1_1 + 3)
;     genIfxJump
;       Peephole 111    removed ljmp by inverse jump logic
	jnb     acc.7,00105$
00116$:
;_fsmul.c:56: result += 0x80;
;     genPlus
	mov	a,#0x80
	add	a,___fsmul_result_1_1
	mov	___fsmul_result_1_1,a
;       Peephole 181    changed mov to clr
	clr     a
	addc	a,(___fsmul_result_1_1 + 1)
	mov	(___fsmul_result_1_1 + 1),a
;       Peephole 181    changed mov to clr
	clr     a
	addc	a,(___fsmul_result_1_1 + 2)
	mov	(___fsmul_result_1_1 + 2),a
;       Peephole 181    changed mov to clr
	clr     a
	addc	a,(___fsmul_result_1_1 + 3)
	mov	(___fsmul_result_1_1 + 3),a
;_fsmul.c:57: result >>= 8;
;     genRightShift
;     genRightShiftLiteral
;     genrshFour
	mov	___fsmul_result_1_1,(___fsmul_result_1_1 + 1)
	mov	(___fsmul_result_1_1 + 1),(___fsmul_result_1_1 + 2)
	mov	(___fsmul_result_1_1 + 2),(___fsmul_result_1_1 + 3)
	mov	(___fsmul_result_1_1 + 3),#0x00
;       Peephole 112.b  changed ljmp to sjmp
	sjmp    00106$
00105$:
;_fsmul.c:62: result += 0x40;
;     genPlus
	mov	a,#0x40
	add	a,___fsmul_result_1_1
	mov	___fsmul_result_1_1,a
;       Peephole 181    changed mov to clr
	clr     a
	addc	a,(___fsmul_result_1_1 + 1)
	mov	(___fsmul_result_1_1 + 1),a
;       Peephole 181    changed mov to clr
	clr     a
	addc	a,(___fsmul_result_1_1 + 2)
	mov	(___fsmul_result_1_1 + 2),a
;       Peephole 181    changed mov to clr
	clr     a
	addc	a,(___fsmul_result_1_1 + 3)
	mov	(___fsmul_result_1_1 + 3),a
;_fsmul.c:63: result >>= 7;
;     genRightShift
;     genRightShiftLiteral
;     genrshFour
	mov	a,(___fsmul_result_1_1 + 1)
	mov	c,acc.7
	xch	a,___fsmul_result_1_1
	rlc	a
	xch	a,___fsmul_result_1_1
	rlc	a
	xch	a,___fsmul_result_1_1
	anl	a,#0x01
	mov	(___fsmul_result_1_1 + 1),a
	mov	a,(___fsmul_result_1_1 + 2)
	add	a,acc
	orl	a,(___fsmul_result_1_1 + 1)
	mov	(___fsmul_result_1_1 + 1),a
	mov	a,(___fsmul_result_1_1 + 3)
	mov	c,acc.7
	xch	a,(___fsmul_result_1_1 + 2)
	rlc	a
	xch	a,(___fsmul_result_1_1 + 2)
	rlc	a
	xch	a,(___fsmul_result_1_1 + 2)
	anl	a,#0x01
	mov	(___fsmul_result_1_1 + 3),a
;_fsmul.c:64: exp--;
;     genMinus
;     genMinusDec
	dec	___fsmul_exp_1_1
	mov	a,#0xff
	cjne	a,___fsmul_exp_1_1,00117$
	dec	(___fsmul_exp_1_1 + 1)
00117$:
00106$:
;_fsmul.c:67: result &= ~HIDDEN;
;     genAnd
	anl	(___fsmul_result_1_1 + 2),#0x7F
;_fsmul.c:70: fl1.l = PACK (sign ? SIGNBIT : 0 , (unsigned long)exp, result);  
;     genIfx
	mov	a,___fsmul_sign_1_1
;     genIfxJump
;       Peephole 110    removed ljmp by inverse jump logic
	jz      00109$
00118$:
;     genAssign
	mov	r2,#0x00
	mov	r3,#0x00
	mov	r4,#0x00
	mov	r5,#0x80
;       Peephole 112.b  changed ljmp to sjmp
	sjmp    00110$
00109$:
;     genAssign
	mov	r2,#0x00
	mov	r3,#0x00
	mov	r4,#0x00
	mov	r5,#0x00
00110$:
;     genCast
	mov	r6,___fsmul_exp_1_1
	mov	r7,(___fsmul_exp_1_1 + 1)
	mov	a,(___fsmul_exp_1_1 + 1)
	rlc	a
	subb	a,acc
	mov	r0,a
	mov	r1,a
;     genLeftShift
;     genLeftShiftLiteral
;     genlshFour
	mov	ar0,r6
	mov	a,r7
	anl	a,#0x01
	mov	c,acc.0
	xch	a,r0
	rrc	a
	xch	a,r0
	rrc	a
	xch	a,r0
	mov	r1,a
;     genOr
;       Peephole 3.c    changed mov to clr
	clr     a
	mov     r7,a
;       Peephole 105    removed redundant mov
	mov     r6,a
	orl	ar2,a
	mov	a,r7
	orl	ar3,a
	mov	a,r0
	orl	ar4,a
	mov	a,r1
	orl	ar5,a
;     genOr
	mov	a,___fsmul_result_1_1
	orl	ar2,a
	mov	a,(___fsmul_result_1_1 + 1)
	orl	ar3,a
	mov	a,(___fsmul_result_1_1 + 2)
	orl	ar4,a
	mov	a,(___fsmul_result_1_1 + 3)
	orl	ar5,a
;     genPointerSet
;     genNearPointerSet
;     genDataPointerSet
	mov	___fsmul_fl1_1_1,r2
	mov	(___fsmul_fl1_1_1 + 1),r3
	mov	(___fsmul_fl1_1_1 + 2),r4
	mov	(___fsmul_fl1_1_1 + 3),r5
;_fsmul.c:71: return (fl1.f);
;     genAssign
;     genRet
	mov	dpl,___fsmul_fl1_1_1
	mov	dph,(___fsmul_fl1_1_1 + 1)
	mov	b,(___fsmul_fl1_1_1 + 2)
	mov	a,(___fsmul_fl1_1_1 + 3)
00107$:
	ret
	.area CSEG    (CODE)
	.area XINIT   (CODE)
