;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.4.0 Tue Oct 12 01:21:31 2004

;--------------------------------------------------------
	.module _strstr
	
	.area CSEG
	.area GSINIT
	.area GSFINAL
	.area XINIT
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl _strstr_PARM_2
	.globl _strstr
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area	OSEG    (OVR)
_strstr_sloc0_1_0::
	.ds 2
_strstr_sloc1_1_0::
	.ds 1
_strstr_sloc2_1_0::
	.ds 2
_strstr_sloc3_1_0::
	.ds 2
_strstr_sloc4_1_0::
	.ds 2
_strstr_sloc5_1_0::
	.ds 1
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
_strstr_PARM_2::
	.ds 2
_strstr_str1_1_1::
	.ds 2
_strstr_cp_1_1::
	.ds 2
_strstr_s2_1_1::
	.ds 2
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area GSINIT
	.area GSFINAL
	.area GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME
	.area CSEG
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG
;------------------------------------------------------------
;Allocation info for local variables in function 'strstr'
;------------------------------------------------------------
;str2                      Allocated with name '_strstr_PARM_2'
;str1                      Allocated with name '_strstr_str1_1_1'
;cp                        Allocated with name '_strstr_cp_1_1'
;s1                        Allocated to registers 
;s2                        Allocated with name '_strstr_s2_1_1'
;sloc0                     Allocated with name '_strstr_sloc0_1_0'
;sloc1                     Allocated with name '_strstr_sloc1_1_0'
;sloc2                     Allocated with name '_strstr_sloc2_1_0'
;sloc3                     Allocated with name '_strstr_sloc3_1_0'
;sloc4                     Allocated with name '_strstr_sloc4_1_0'
;sloc5                     Allocated with name '_strstr_sloc5_1_0'
;------------------------------------------------------------
;_strstr.c:26: char * strstr (
;	-----------------------------------------
;	 function strstr
;	-----------------------------------------
_strstr:
;     genReceive
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, EXT(_strstr_str1_1_1), 0), stacked=0, isaddr=0
	sta	(_strstr_str1_1_1 + 1)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, EXT(_strstr_str1_1_1), 1), stacked=0, isaddr=0
	stx	_strstr_str1_1_1
;_strstr.c:31: char * cp = str1;
;     genAssign
;     loadRegFromAop (a, EXT(_strstr_str1_1_1), 0)
	lda	(_strstr_str1_1_1 + 1)
;     storeRegToAop (a, EXT(_strstr_cp_1_1), 0), stacked=0, isaddr=0
	sta	(_strstr_cp_1_1 + 1)
;     loadRegFromAop (a, EXT(_strstr_str1_1_1), 1)
	lda	_strstr_str1_1_1
;     storeRegToAop (a, EXT(_strstr_cp_1_1), 1), stacked=0, isaddr=0
	sta	_strstr_cp_1_1
;_strstr.c:35: if ( !*str2 )
;     genAssign
;     loadRegFromAop (a, EXT(_strstr_PARM_2), 0)
	lda	(_strstr_PARM_2 + 1)
;     storeRegToAop (a, DIR(_strstr_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(_strstr_sloc0_1_0 + 1)
;     loadRegFromAop (a, EXT(_strstr_PARM_2), 1)
	lda	_strstr_PARM_2
;     storeRegToAop (a, DIR(_strstr_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*_strstr_sloc0_1_0
;     genPointerGet
;     genFarPointerGet
;     loadRegFromAop (hx, DIR(_strstr_sloc0_1_0), 0)
	ldhx	*_strstr_sloc0_1_0
	lda	,x
;     storeRegToAop (a, DIR(_strstr_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*_strstr_sloc1_1_0
;     genIfx
	tst	*_strstr_sloc1_1_0
;     genIfxJump
; Peephole 2c	- eliminated jmp
	bne	00122$
00123$:
;_strstr.c:36: return str1;
;     genRet
;     loadRegFromAop (x, EXT(_strstr_str1_1_1), 1)
	ldx	_strstr_str1_1_1
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(_strstr_str1_1_1), 0)
	lda	(_strstr_str1_1_1 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
	jmp	00113$
;_strstr.c:38: while (*cp)
00122$:
;     genAssign
;     loadRegFromAop (a, EXT(_strstr_str1_1_1), 0)
	lda	(_strstr_str1_1_1 + 1)
;     storeRegToAop (a, DIR(_strstr_sloc2_1_0), 0), stacked=0, isaddr=0
	sta	*(_strstr_sloc2_1_0 + 1)
;     loadRegFromAop (a, EXT(_strstr_str1_1_1), 1)
	lda	_strstr_str1_1_1
;     storeRegToAop (a, DIR(_strstr_sloc2_1_0), 1), stacked=0, isaddr=0
	sta	*_strstr_sloc2_1_0
00110$:
;     genPointerGet
;     genFarPointerGet
;     loadRegFromAop (hx, DIR(_strstr_sloc2_1_0), 0)
	ldhx	*_strstr_sloc2_1_0
	lda	,x
;     storeRegToAop (a, DIR(_strstr_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*_strstr_sloc1_1_0
;     genIfx
	tst	*_strstr_sloc1_1_0
;     genIfxJump
	bne	00124$
	jmp	00112$
00124$:
;_strstr.c:41: s2 = str2;
;     genAssign
;     loadRegFromAop (a, DIR(_strstr_sloc0_1_0), 0)
	lda	*(_strstr_sloc0_1_0 + 1)
;     storeRegToAop (a, EXT(_strstr_s2_1_1), 0), stacked=0, isaddr=0
	sta	(_strstr_s2_1_1 + 1)
;     loadRegFromAop (a, DIR(_strstr_sloc0_1_0), 1)
	lda	*_strstr_sloc0_1_0
;     storeRegToAop (a, EXT(_strstr_s2_1_1), 1), stacked=0, isaddr=0
	sta	_strstr_s2_1_1
;_strstr.c:43: while ( *s1 && *s2 && !(*s1-*s2) )
;     genAssign
	mov	*(_strstr_sloc2_1_0 + 1),*(_strstr_sloc3_1_0 + 1)
	mov	*_strstr_sloc2_1_0,*_strstr_sloc3_1_0
;     genAssign
;     loadRegFromAop (a, EXT(_strstr_s2_1_1), 0)
	lda	(_strstr_s2_1_1 + 1)
;     storeRegToAop (a, DIR(_strstr_sloc4_1_0), 0), stacked=0, isaddr=0
	sta	*(_strstr_sloc4_1_0 + 1)
;     loadRegFromAop (a, EXT(_strstr_s2_1_1), 1)
	lda	_strstr_s2_1_1
;     storeRegToAop (a, DIR(_strstr_sloc4_1_0), 1), stacked=0, isaddr=0
	sta	*_strstr_sloc4_1_0
00105$:
;     genPointerGet
;     genFarPointerGet
;     loadRegFromAop (hx, DIR(_strstr_sloc3_1_0), 0)
	ldhx	*_strstr_sloc3_1_0
	lda	,x
;     storeRegToAop (a, DIR(_strstr_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*_strstr_sloc1_1_0
;     genIfx
	tst	*_strstr_sloc1_1_0
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00107$
00125$:
;     genPointerGet
;     genFarPointerGet
;     loadRegFromAop (hx, DIR(_strstr_sloc4_1_0), 0)
	ldhx	*_strstr_sloc4_1_0
	lda	,x
;     storeRegToAop (a, DIR(_strstr_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*_strstr_sloc1_1_0
;     genIfx
	tst	*_strstr_sloc1_1_0
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00107$
00126$:
;     genPointerGet
;     genFarPointerGet
;     loadRegFromAop (hx, DIR(_strstr_sloc3_1_0), 0)
	ldhx	*_strstr_sloc3_1_0
	lda	,x
;     storeRegToAop (a, DIR(_strstr_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*_strstr_sloc1_1_0
;     genPointerGet
;     genFarPointerGet
;     loadRegFromAop (hx, DIR(_strstr_sloc4_1_0), 0)
	ldhx	*_strstr_sloc4_1_0
	lda	,x
;     storeRegToAop (a, DIR(_strstr_sloc5_1_0), 0), stacked=0, isaddr=0
	sta	*_strstr_sloc5_1_0
;     genDjnz
;     genMinus
;     loadRegFromAop (a, DIR(_strstr_sloc1_1_0), 0)
	lda	*_strstr_sloc1_1_0
	sub	*_strstr_sloc5_1_0
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     genIfx
	tsta
;     genIfxJump
; Peephole 2c	- eliminated jmp
	bne	00107$
00127$:
; forgot to free a
;_strstr.c:44: s1++, s2++;
; checking lic
; checking IS_ITEMP
; pset=0, pget=0
;     genPlus
; IS_AOP_HX = 0
;     loadRegFromAop (hx, DIR(_strstr_sloc3_1_0), 0)
	ldhx	*_strstr_sloc3_1_0
	aix	#1
;     storeRegToAop (hx, DIR(_strstr_sloc3_1_0), 0), stacked=0, isaddr=0
	sthx	*_strstr_sloc3_1_0
; checking lic
; checking IS_ITEMP
; pset=0, pget=0
;     genPlus
; IS_AOP_HX = 0
;     loadRegFromAop (hx, DIR(_strstr_sloc4_1_0), 0)
	ldhx	*_strstr_sloc4_1_0
	aix	#1
;     storeRegToAop (hx, DIR(_strstr_sloc4_1_0), 0), stacked=0, isaddr=0
	sthx	*_strstr_sloc4_1_0
; Peephole 3	- shortened jmp to bra
	bra	00105$
00107$:
;_strstr.c:46: if (!*s2)
;     genPointerGet
;     genFarPointerGet
;     loadRegFromAop (hx, DIR(_strstr_sloc4_1_0), 0)
	ldhx	*_strstr_sloc4_1_0
	lda	,x
;     storeRegToAop (a, DIR(_strstr_sloc5_1_0), 0), stacked=0, isaddr=0
	sta	*_strstr_sloc5_1_0
;     genIfx
	tst	*_strstr_sloc5_1_0
;     genIfxJump
; Peephole 2c	- eliminated jmp
	bne	00109$
00128$:
;_strstr.c:47: return(cp);
;     genRet
;     loadRegFromAop (x, EXT(_strstr_cp_1_1), 1)
	ldx	_strstr_cp_1_1
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(_strstr_cp_1_1), 0)
	lda	(_strstr_cp_1_1 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 3	- shortened jmp to bra
	bra	00113$
00109$:
;_strstr.c:49: cp++;
; checking lic
; checking IS_ITEMP
; pset=0, pget=0
;     genPlus
; IS_AOP_HX = 0
;     loadRegFromAop (hx, DIR(_strstr_sloc2_1_0), 0)
	ldhx	*_strstr_sloc2_1_0
	aix	#1
;     storeRegToAop (hx, DIR(_strstr_sloc2_1_0), 0), stacked=0, isaddr=0
	sthx	*_strstr_sloc2_1_0
;     genAssign
;     loadRegFromAop (a, DIR(_strstr_sloc2_1_0), 0)
	lda	*(_strstr_sloc2_1_0 + 1)
;     storeRegToAop (a, EXT(_strstr_cp_1_1), 0), stacked=0, isaddr=0
	sta	(_strstr_cp_1_1 + 1)
;     loadRegFromAop (a, DIR(_strstr_sloc2_1_0), 1)
	lda	*_strstr_sloc2_1_0
;     storeRegToAop (a, EXT(_strstr_cp_1_1), 1), stacked=0, isaddr=0
	sta	_strstr_cp_1_1
	jmp	00110$
00112$:
;_strstr.c:52: return (NULL) ;
;     genRet
;     loadRegFromAop (x, LIT(#0x00), 1)
	ldx	#0x00
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, LIT(#0x00), 0)
	lda	#0x00
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00113$:
	rts
	.area CSEG
	.area XINIT
