;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.4.0 Tue Oct 12 01:18:39 2004

;--------------------------------------------------------
	.module logf
	.optsdcc -mmcs51 --model-small
	
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl _logf
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
;--------------------------------------------------------
; special function bits 
;--------------------------------------------------------
;--------------------------------------------------------
; overlayable register banks 
;--------------------------------------------------------
	.area REG_BANK_0	(REL,OVR,DATA)
	.ds 8
;--------------------------------------------------------
; internal ram data
;--------------------------------------------------------
	.area DSEG    (DATA)
;--------------------------------------------------------
; overlayable items in internal ram 
;--------------------------------------------------------
	.area OSEG    (OVR,DATA)
;--------------------------------------------------------
; indirectly addressable internal ram data
;--------------------------------------------------------
	.area ISEG    (DATA)
;--------------------------------------------------------
; bit data
;--------------------------------------------------------
	.area BSEG    (BIT)
;--------------------------------------------------------
; external ram data
;--------------------------------------------------------
	.area XSEG    (XDATA)
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG   (XDATA)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area GSINIT  (CODE)
	.area GSFINAL (CODE)
	.area GSINIT  (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME    (CODE)
	.area CSEG    (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG    (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function 'logf'
;------------------------------------------------------------
;x                         Allocated to registers r2 r3 r4 r5 
;Rz                        Allocated to stack - offset 1
;f                         Allocated to registers r2 r3 r4 r5 
;z                         Allocated to stack - offset 5
;w                         Allocated to stack - offset 9
;znum                      Allocated to stack - offset 13
;zden                      Allocated to registers r2 r3 r4 r5 
;xn                        Allocated to stack - offset 17
;n                         Allocated to stack - offset 21
;sloc0                     Allocated to stack - offset 23
;------------------------------------------------------------
;logf.c:37: float logf(const float x) reentrant
;	-----------------------------------------
;	 function logf
;	-----------------------------------------
_logf:
	ar2 = 0x02
	ar3 = 0x03
	ar4 = 0x04
	ar5 = 0x05
	ar6 = 0x06
	ar7 = 0x07
	ar0 = 0x00
	ar1 = 0x01
	push	_bp
	mov	_bp,sp
	mov	r0,a
	mov	a,sp
	add	a,#0x1a
	mov	sp,a
	mov	a,r0
;     genReceive
;logf.c:47: if (x<=0.0)
;     genAssign
;     genCall
	mov     r2,dpl
	mov     r3,dph
	mov     r4,b
	mov     r5,a
	mov     ___fsgt_PARM_2,#0x00
	mov     (___fsgt_PARM_2 + 1),#0x00
	mov     (___fsgt_PARM_2 + 2),#0x00
	mov     (___fsgt_PARM_2 + 3),#0x00
;       Peephole 238.a  removed 4 redundant moves
	push	ar2
	push	ar3
	push	ar4
	push	ar5
	lcall	___fsgt
	mov	a,dpl
	pop	ar5
	pop	ar4
	pop	ar3
	pop	ar2
;     genIfx
;     genIfxJump
;       Peephole 109    removed ljmp by inverse jump logic
	jnz     00102$
00110$:
;logf.c:49: errno=EDOM;
;     genAssign
	clr	a
	mov	(_errno + 1),a
	mov	_errno,#0x21
;logf.c:50: return 0.0;
;     genRet
	mov	dpl,#0x00
;       Peephole 3.a    changed mov to clr
;       Peephole 3.b    changed mov to clr
	clr     a
	mov     dph,a
	mov     b,a
	ljmp	00106$
00102$:
;logf.c:52: f=frexpf(x, &n);
;     genAddrOf
	mov	a,_bp
	add	a,#0x15
	mov	r6,a
;     genCast
	mov	_frexpf_PARM_2,r6
	mov	(_frexpf_PARM_2 + 1),#0x00
	mov	(_frexpf_PARM_2 + 2),#0x0
;     genCall
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	mov	a,r5
	lcall	_frexpf
;     genAssign
;logf.c:53: znum=f-0.5;
;     genAssign
;     genCall
	mov     r2,dpl
	mov     r3,dph
	mov     r4,b
	mov     r5,a
	mov     ___fssub_PARM_2,#0x00
	mov     (___fssub_PARM_2 + 1),#0x00
	mov     (___fssub_PARM_2 + 2),#0x00
	mov     (___fssub_PARM_2 + 3),#0x3F
;       Peephole 238.a  removed 4 redundant moves
	push	ar2
	push	ar3
	push	ar4
	push	ar5
	lcall	___fssub
	push	acc
	mov	a,_bp
	add	a,#0x0d
	mov	r0,a
	pop	acc
	mov	@r0,dpl
	inc	r0
	mov	@r0,dph
	inc	r0
	mov	@r0,b
	inc	r0
	mov	@r0,a
	pop	ar5
	pop	ar4
	pop	ar3
	pop	ar2
;     genAssign
	mov	a,_bp
	add	a,#0x0d
	mov	r0,a
;logf.c:54: if (f>C0)
;     genAssign
	mov	___fsgt_PARM_2,#0xF3
	mov	(___fsgt_PARM_2 + 1),#0x04
	mov	(___fsgt_PARM_2 + 2),#0x35
	mov	(___fsgt_PARM_2 + 3),#0x3F
;     genCall
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	mov	a,r5
	push	ar2
	push	ar3
	push	ar4
	push	ar5
	lcall	___fsgt
	mov	a,dpl
	pop	ar5
	pop	ar4
	pop	ar3
	pop	ar2
;     genIfx
;     genIfxJump
	jnz	00111$
	ljmp	00104$
00111$:
;logf.c:56: znum-=0.5;
;     genAssign
	mov	___fssub_PARM_2,#0x00
	mov	(___fssub_PARM_2 + 1),#0x00
	mov	(___fssub_PARM_2 + 2),#0x00
	mov	(___fssub_PARM_2 + 3),#0x3F
;     genCall
	mov	a,_bp
	add	a,#0x0d
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	inc	r0
	mov	a,@r0
	push	ar2
	push	ar3
	push	ar4
	push	ar5
	lcall	___fssub
	push	acc
	mov	a,_bp
	add	a,#0x17
	mov	r0,a
	pop	acc
	mov	@r0,dpl
	inc	r0
	mov	@r0,dph
	inc	r0
	mov	@r0,b
	inc	r0
	mov	@r0,a
	pop	ar5
	pop	ar4
	pop	ar3
	pop	ar2
;     genAssign
	mov	a,_bp
	add	a,#0x17
	mov	r0,a
	mov	a,_bp
	add	a,#0x0d
	mov	r1,a
	mov	a,@r0
	mov	@r1,a
	inc	r0
	inc	r1
	mov	a,@r0
	mov	@r1,a
	inc	r0
	inc	r1
	mov	a,@r0
	mov	@r1,a
	inc	r0
	inc	r1
	mov	a,@r0
	mov	@r1,a
;logf.c:57: zden=(f*0.5)+0.5;
;     genAssign
	mov	___fsmul_PARM_2,#0x00
	mov	(___fsmul_PARM_2 + 1),#0x00
	mov	(___fsmul_PARM_2 + 2),#0x00
	mov	(___fsmul_PARM_2 + 3),#0x3F
;     genCall
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	mov	a,r5
	lcall	___fsmul
;     genAssign
;     genCall
	mov     r4,dpl
	mov     r5,dph
	mov     r2,b
	mov     r3,a
	mov     ___fsadd_PARM_2,#0x00
	mov     (___fsadd_PARM_2 + 1),#0x00
	mov     (___fsadd_PARM_2 + 2),#0x00
	mov     (___fsadd_PARM_2 + 3),#0x3F
;       Peephole 238.a  removed 4 redundant moves
	lcall	___fsadd
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	mov	r5,a
;     genAssign
;       Peephole 112.b  changed ljmp to sjmp
	sjmp    00105$
00104$:
;logf.c:61: n--;
;     genMinus
	mov	a,_bp
	add	a,#0x15
	mov	r0,a
;     genMinusDec
	mov	a,@r0
	add	a,#0xff
	mov	@r0,a
	inc	r0
	mov	a,@r0
	addc	a,#0xff
	mov	@r0,a
;logf.c:62: zden=znum*0.5+0.5;
;     genAssign
	mov	___fsmul_PARM_2,#0x00
	mov	(___fsmul_PARM_2 + 1),#0x00
	mov	(___fsmul_PARM_2 + 2),#0x00
	mov	(___fsmul_PARM_2 + 3),#0x3F
;     genCall
	mov	a,_bp
	add	a,#0x0d
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	inc	r0
	mov	a,@r0
	lcall	___fsmul
;     genAssign
;     genCall
	mov     r2,dpl
	mov     r3,dph
	mov     r4,b
	mov     r5,a
	mov     ___fsadd_PARM_2,#0x00
	mov     (___fsadd_PARM_2 + 1),#0x00
	mov     (___fsadd_PARM_2 + 2),#0x00
	mov     (___fsadd_PARM_2 + 3),#0x3F
;       Peephole 238.a  removed 4 redundant moves
	lcall	___fsadd
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	mov	r5,a
;     genAssign
00105$:
;logf.c:64: z=znum/zden;
;     genAssign
	mov	___fsdiv_PARM_2,r2
	mov	(___fsdiv_PARM_2 + 1),r3
	mov	(___fsdiv_PARM_2 + 2),r4
	mov	(___fsdiv_PARM_2 + 3),r5
;     genCall
	mov	a,_bp
	add	a,#0x0d
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	inc	r0
	mov	a,@r0
	lcall	___fsdiv
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	mov	r5,a
;     genAssign
	mov	a,_bp
	add	a,#0x05
	mov	r0,a
	mov	@r0,ar2
	inc	r0
	mov	@r0,ar3
	inc	r0
	mov	@r0,ar4
	inc	r0
	mov	@r0,ar5
;logf.c:65: w=z*z;
;     genAssign
	mov	a,_bp
	add	a,#0x05
	mov	r0,a
	mov	___fsmul_PARM_2,@r0
	inc	r0
	mov	(___fsmul_PARM_2 + 1),@r0
	inc	r0
	mov	(___fsmul_PARM_2 + 2),@r0
	inc	r0
	mov	(___fsmul_PARM_2 + 3),@r0
;     genCall
	mov	a,_bp
	add	a,#0x05
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	inc	r0
	mov	a,@r0
	lcall	___fsmul
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	mov	r5,a
;     genAssign
	mov	a,_bp
	add	a,#0x09
	mov	r0,a
	mov	@r0,ar2
	inc	r0
	mov	@r0,ar3
	inc	r0
	mov	@r0,ar4
	inc	r0
	mov	@r0,ar5
;logf.c:67: Rz=z+z*(w*A(w)/B(w));
;     genAssign
	mov	___fsmul_PARM_2,#0x3D
	mov	(___fsmul_PARM_2 + 1),#0x7E
	mov	(___fsmul_PARM_2 + 2),#0x0D
	mov	(___fsmul_PARM_2 + 3),#0xBF
;     genCall
	mov	a,_bp
	add	a,#0x09
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	inc	r0
	mov	a,@r0
	lcall	___fsmul
	mov	r6,dpl
	mov	r7,dph
	mov	r2,b
	mov	r3,a
;     genAssign
	mov	___fsadd_PARM_2,#0x3A
	mov	(___fsadd_PARM_2 + 1),#0x3F
	mov	(___fsadd_PARM_2 + 2),#0xD4
	mov	(___fsadd_PARM_2 + 3),#0xC0
;     genCall
	mov	a,_bp
	add	a,#0x09
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	inc	r0
	mov	a,@r0
	push	ar2
	push	ar3
	push	ar6
	push	ar7
	lcall	___fsadd
	mov	___fsdiv_PARM_2,dpl
	mov	(___fsdiv_PARM_2 + 1),dph
	mov	(___fsdiv_PARM_2 + 2),b
	mov	(___fsdiv_PARM_2 + 3),a
	pop	ar7
	pop	ar6
	pop	ar3
	pop	ar2
;     genCall
	mov	dpl,r6
	mov	dph,r7
	mov	b,r2
	mov	a,r3
	lcall	___fsdiv
	mov	___fsmul_PARM_2,dpl
	mov	(___fsmul_PARM_2 + 1),dph
	mov	(___fsmul_PARM_2 + 2),b
	mov	(___fsmul_PARM_2 + 3),a
;     genCall
	mov	a,_bp
	add	a,#0x05
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	inc	r0
	mov	a,@r0
	lcall	___fsmul
	mov	___fsadd_PARM_2,dpl
	mov	(___fsadd_PARM_2 + 1),dph
	mov	(___fsadd_PARM_2 + 2),b
	mov	(___fsadd_PARM_2 + 3),a
;     genCall
	mov	a,_bp
	add	a,#0x05
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	inc	r0
	mov	a,@r0
	lcall	___fsadd
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	mov	r5,a
;     genAssign
;       Peephole 212    reduced add sequence to inc
	mov     r0,_bp
	inc     r0
	mov	@r0,ar2
	inc	r0
	mov	@r0,ar3
	inc	r0
	mov	@r0,ar4
	inc	r0
	mov	@r0,ar5
;logf.c:68: xn=n;
;     genCall
	mov	a,_bp
	add	a,#0x15
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	lcall	___sint2fs
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	mov	r5,a
;     genAssign
	mov	a,_bp
	add	a,#0x11
	mov	r0,a
	mov	@r0,ar2
	inc	r0
	mov	@r0,ar3
	inc	r0
	mov	@r0,ar4
	inc	r0
	mov	@r0,ar5
;logf.c:69: return ((xn*C2+Rz)+xn*C1);
;     genAssign
	mov	___fsmul_PARM_2,#0x83
	mov	(___fsmul_PARM_2 + 1),#0x80
	mov	(___fsmul_PARM_2 + 2),#0x5E
	mov	(___fsmul_PARM_2 + 3),#0xB9
;     genCall
	mov	a,_bp
	add	a,#0x11
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	inc	r0
	mov	a,@r0
	lcall	___fsmul
	mov	r6,dpl
	mov	r7,dph
	mov	r2,b
	mov	r3,a
;     genAssign
;       Peephole 212    reduced add sequence to inc
	mov     r0,_bp
	inc     r0
	mov	___fsadd_PARM_2,@r0
	inc	r0
	mov	(___fsadd_PARM_2 + 1),@r0
	inc	r0
	mov	(___fsadd_PARM_2 + 2),@r0
	inc	r0
	mov	(___fsadd_PARM_2 + 3),@r0
;     genCall
	mov	dpl,r6
	mov	dph,r7
	mov	b,r2
	mov	a,r3
	lcall	___fsadd
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	mov	r5,a
;     genAssign
	mov	___fsmul_PARM_2,#0x00
	mov	(___fsmul_PARM_2 + 1),#0x80
	mov	(___fsmul_PARM_2 + 2),#0x31
	mov	(___fsmul_PARM_2 + 3),#0x3F
;     genCall
	mov	a,_bp
	add	a,#0x11
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	inc	r0
	mov	a,@r0
	push	ar2
	push	ar3
	push	ar4
	push	ar5
	lcall	___fsmul
	mov	___fsadd_PARM_2,dpl
	mov	(___fsadd_PARM_2 + 1),dph
	mov	(___fsadd_PARM_2 + 2),b
	mov	(___fsadd_PARM_2 + 3),a
	pop	ar5
	pop	ar4
	pop	ar3
	pop	ar2
;     genCall
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	mov	a,r5
	lcall	___fsadd
;     genRet
;       Peephole 191    removed redundant mov
	mov     r2,dpl
	mov     r3,dph
	mov     r4,b
	mov     r5,a
;       Peephole 238.b  removed 3 redundant moves
00106$:
	mov	sp,_bp
	pop	_bp
	ret
	.area CSEG    (CODE)
	.area XINIT   (CODE)
