;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.4.0 Tue Oct 12 01:21:23 2004

;--------------------------------------------------------
	.module _divsint
	
	.area CSEG
	.area GSINIT
	.area GSFINAL
	.area XINIT
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl __divsint_PARM_2
	.globl __divsint
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
__divsint_sloc0_1_0::
	.ds 2
__divsint_sloc1_1_0::
	.ds 2
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area OSEG    (OVR)
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
__divsint_PARM_2::
	.ds 2
__divsint_a_1_1::
	.ds 2
__divsint_r_1_1::
	.ds 2
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area GSINIT
	.area GSFINAL
	.area GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME
	.area CSEG
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG
;------------------------------------------------------------
;Allocation info for local variables in function '_divsint'
;------------------------------------------------------------
;sloc0                     Allocated with name '__divsint_sloc0_1_0'
;sloc1                     Allocated with name '__divsint_sloc1_1_0'
;b                         Allocated with name '__divsint_PARM_2'
;a                         Allocated with name '__divsint_a_1_1'
;r                         Allocated with name '__divsint_r_1_1'
;------------------------------------------------------------
;_divsint.c:206: _divsint (int a, int b)
;	-----------------------------------------
;	 function _divsint
;	-----------------------------------------
__divsint:
;     genReceive
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, EXT(__divsint_a_1_1), 0), stacked=0, isaddr=0
	sta	(__divsint_a_1_1 + 1)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, EXT(__divsint_a_1_1), 1), stacked=0, isaddr=0
	stx	__divsint_a_1_1
;_divsint.c:210: r = _divuint((a < 0 ? -a : a),
;     genCmpLt
;     genCmp
;     loadRegFromAop (a, EXT(__divsint_a_1_1), 1)
	lda	__divsint_a_1_1
	rola
;     genIfxJump
; Peephole 2a	- eliminated jmp
	bcc	00106$
00113$:
;     genUminus
	clra
	sub	(__divsint_a_1_1 + 1)
;     storeRegToAop (a, DIR(__divsint_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(__divsint_sloc0_1_0 + 1)
	clra
	sbc	__divsint_a_1_1
;     storeRegToAop (a, DIR(__divsint_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*__divsint_sloc0_1_0
; Peephole 3	- shortened jmp to bra
	bra	00107$
00106$:
;     genAssign
;     loadRegFromAop (a, EXT(__divsint_a_1_1), 0)
	lda	(__divsint_a_1_1 + 1)
;     storeRegToAop (a, DIR(__divsint_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(__divsint_sloc0_1_0 + 1)
;     loadRegFromAop (a, EXT(__divsint_a_1_1), 1)
	lda	__divsint_a_1_1
;     storeRegToAop (a, DIR(__divsint_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*__divsint_sloc0_1_0
00107$:
;     genAssign
;_divsint.c:211: (b < 0 ? -b : b));
;     genCmpLt
;     genCmp
;     loadRegFromAop (a, EXT(__divsint_PARM_2), 1)
	lda	__divsint_PARM_2
	rola
;     genIfxJump
; Peephole 2a	- eliminated jmp
	bcc	00108$
00114$:
;     genUminus
	clra
	sub	(__divsint_PARM_2 + 1)
;     storeRegToAop (a, DIR(__divsint_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__divsint_sloc1_1_0 + 1)
	clra
	sbc	__divsint_PARM_2
;     storeRegToAop (a, DIR(__divsint_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*__divsint_sloc1_1_0
; Peephole 3	- shortened jmp to bra
	bra	00109$
00108$:
;     genAssign
;     loadRegFromAop (a, EXT(__divsint_PARM_2), 0)
	lda	(__divsint_PARM_2 + 1)
;     storeRegToAop (a, DIR(__divsint_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__divsint_sloc1_1_0 + 1)
;     loadRegFromAop (a, EXT(__divsint_PARM_2), 1)
	lda	__divsint_PARM_2
;     storeRegToAop (a, DIR(__divsint_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*__divsint_sloc1_1_0
00109$:
;     genAssign
;     loadRegFromAop (a, DIR(__divsint_sloc1_1_0), 0)
	lda	*(__divsint_sloc1_1_0 + 1)
;     storeRegToAop (a, EXT(__divuint_PARM_2), 0), stacked=0, isaddr=1
	sta	(__divuint_PARM_2 + 1)
;     loadRegFromAop (a, DIR(__divsint_sloc1_1_0), 1)
	lda	*__divsint_sloc1_1_0
;     storeRegToAop (a, EXT(__divuint_PARM_2), 1), stacked=0, isaddr=1
	sta	__divuint_PARM_2
;     genCall
;     loadRegFromAop (x, DIR(__divsint_sloc0_1_0), 1)
	ldx	*__divsint_sloc0_1_0
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, DIR(__divsint_sloc0_1_0), 0)
	lda	*(__divsint_sloc0_1_0 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
	jsr	__divuint
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, EXT(__divsint_r_1_1), 0), stacked=0, isaddr=0
	sta	(__divsint_r_1_1 + 1)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, EXT(__divsint_r_1_1), 1), stacked=0, isaddr=0
	stx	__divsint_r_1_1
;_divsint.c:212: if ( (a < 0) ^ (b < 0))
;     genCmpLt
;     genCmp
;     loadRegFromAop (a, EXT(__divsint_a_1_1), 1)
	lda	__divsint_a_1_1
	rola
	clra
	rola
;     storeRegToAop (a, DIR(__divsint_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*__divsint_sloc1_1_0
;     genCmpLt
;     genCmp
;     loadRegFromAop (a, EXT(__divsint_PARM_2), 1)
	lda	__divsint_PARM_2
	rola
	clra
	rola
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     genXor
;     loadRegFromAop (a, REG(-,-,x,a), 0)
; transferRegReg(a,a)
	eor	*__divsint_sloc1_1_0
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     genIfx
	tsta
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00102$
00115$:
; forgot to free a
;_divsint.c:213: return -r;
;     genUminus
	clra
	sub	(__divsint_r_1_1 + 1)
;     storeRegToAop (a, DIR(__divsint_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__divsint_sloc1_1_0 + 1)
	clra
	sbc	__divsint_r_1_1
;     storeRegToAop (a, DIR(__divsint_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*__divsint_sloc1_1_0
;     genRet
;     loadRegFromAop (x, DIR(__divsint_sloc1_1_0), 1)
	ldx	*__divsint_sloc1_1_0
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, DIR(__divsint_sloc1_1_0), 0)
	lda	*(__divsint_sloc1_1_0 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 3	- shortened jmp to bra
	bra	00104$
00102$:
;_divsint.c:215: return r;
;     genRet
;     loadRegFromAop (x, EXT(__divsint_r_1_1), 1)
	ldx	__divsint_r_1_1
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(__divsint_r_1_1), 0)
	lda	(__divsint_r_1_1 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00104$:
	rts
	.area CSEG
	.area XINIT
