Scicos Block
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##
Discrete time delay

### Contents

- Discrete time delay
  - Palette
  - Description
  - Dialog box
  - Default properties
  - Interfacing function
  - Compiled Super Block content

### Palette

- OldBlocks - Old blocks palette

### Description

This compiled super-block implements a discretized delay It is build with a shift register and a clock. The value of the delay is given by the discretization time step multiplied by the number-1 of state of the register.

### Dialog box

- Discretization time step
  Set the time period of the integrated clock.
  Properties : Type 'vec' of size 1.

- Register initial state
  Set the length and the initial conditions of the register.
  Properties : Type 'vec' of size -1.

### Default properties

- always active: no
- direct-feedthrough: no
- zero-crossing: no
- mode: no
- regular inputs:
  - port 1 : size [1,1] / type 1
- regular outputs:
  - port 1 : size [1,1] / type 1
- number/sizes of activation inputs: 0
- number/sizes of activation outputs: 0
- continuous-time state: no
- discrete-time state: no
- object discrete-time state: no
- name of computational function: csuper

### Interfacing function

- SCI/macros/scicos_blocks/Linear/DELAY_f.sci [view code]

### Compiled Super Block content