## 3.21 `U`: Logic Device

### 3.21.1 Syntax

`U` xxxxxxx out gnd vdd enable in1 in2 ... family gatetype

### 3.21.2 Purpose

Logic element for mixed or logic mode simulation.

### 3.21.3 Comments

A sample 2 input nand gate might be: `U102 5 0 34 34 2 3 cmos nand`. The input pins are connected to nodes 2 and 3. The output is at node 5. Node 34 is the power supply.
The logic element behaves differently depending on the options `analog`, `mixed`, or `digital`. You set one of these with the `options` command. `Analog` mode substitutes a subcircuit for the gate for full analog simulation. `Digital` mode simulates the gate as a digital device as in an event driven gate level logic simulator. `Mixed` mode applies heuristics to decide whether to use analog or digital for each gate.
In `analog` mode the logic (`U`) device is almost the same as a subcircuit (`X`). The subcircuit is user defined for each gate type used. A `.subckt` defines the analog equivalent of a logic element. The name of the subcircuit is made by concatenating the family, gatetype, and the number of inputs. For example, if the family is `cmos` and the gatetype is `nand` and it has two inputs, the name of the subcircuit is `cmosnand2`. So, the gate in the first paragraph becomes equivalent to: `X 5 0 34 34 2 3 cmosnand2`. You then need to define the subcircuit using the standard `.subckt` notation. You can probe the internal elements the same as an ordinary subcircuit.
The `digital` mode uses simple boolean expressions to compute the output, just like a gate level logic simulator. In this case the output is computed by L(5) = not(L(2) and L(3)) where L(2) is the logic state at node 2. The simulator exploits latency so it will only compute the output if one of the inputs changes. The output actually changes after a delay, specified in the `.model` statement. There are no conversions between digital and analog where gates connect together. There will be an automatic conversion from analog to digital for any input that is driven by an analog device. There will be an automatic conversion from digital to analog for any output that drives an analog device. These conversions will only be done if they are needed. You can probe the analog value at any node. The probe will automatically request the conversion if it needs it. There is no internal subcircuit so it is an error to probe the internal elements.
The `mixed` mode is a combination of analog and digital modes on a gate by gate basis. Some gates will be analog. Some will be digital. This will change as the simulation runs based on the quality of the signals. You need to specify a `.subckt` as you do for the analog mode, but the simulator may not use it. You can usually not probe the elements inside the subcircuit because they come and go.

### 3.21.4 Element Parameters

Family refers to the logic family `.model` statement.
Gatetype is the type of logic gate:

`AND`
`NAND`
`OR`
`NOR`
`XOR`
`INV`

### 3.21.5 Model Parameters

#### Parameters used in digital mode

`DElay` = x
  Propagation delay. (Seconds) (Default = 1e-9) The propagation delay of a simple gate when simulated in logic mode.

#### Parameters used in conversion both ways

`VMAx` = x
  Nominal logic 1. (Volts) (Default = 5.) The nominal value for a logic 1.
`VMIn` = x
  Nominal logic 0. (Volts) (Default = 0.) The nominal value for a logic 0.
`Unknown` = x
  Nominal logic unknown. (Volts) (Default = (vmax+vmin)/2) The output voltage for a logic unknown. In a real circuit, this voltage is unknown, but a simulator needs something, so here it is.

#### Digital to Analog conversion

`RIse` = x
  Rise time. (Seconds) (Default = delay / 2) The nominal rise time of a logic signal. This will be the rise time when a logic signal is converted to analog.
`FAll` = x
  Fall time. (Seconds) (Default = delay / 2) The nominal fall time of a logic signal. This will be the fall time when a logic signal is converted to analog.
`RS` = x
  Series resistance, strong. (Ohms) (Default = 100.) The resistance in series with the output when a logic gate drives analog circuitry.
`RW` = x
  Series resistance, weak. (Ohms) (Default = 1e9) The output resistance in a high impedance state.

#### Analog to Digital conversion

`THH` = x
  Threshold high. (Unitless) (Default = .75) The threshold for the input to cross from transition to high expressed as a fraction of the difference between high and low values. (Low = 0. High = 1.)
`THL` = x
  Threshold low. (Unitless) (Default = .25) The threshold for the input to cross from transition to low expressed as a fraction of the difference between high and low values. (Low = 0. High = 1.)

#### Mode decision parameters

`MR` = x
  Margin rising. (Unitless) (Default = 5) How much worse than nominal the analog input rise time can be and still be accepted as clean enough for logic simulation.
`MF` = x
  Margin falling. (Unitless) (Default = 5) How much worse than nominal the analog input fall time can be and still be accepted as clean enough for logic simulation.
`OVer` = x
  Overshoot limit. (Unitless) (Default = .1) How much overshoot can a signal have and still be accepted as clean enough for logic simulation, expressed as a fraction of the difference between high and low values. (Low = 0. High = 1.)

### 3.21.6 Probes

`V`
  Output voltage.

In this release, there are no probes available in AC analysis except for the internal elements. Internal elements in the analog model are available, but they come and go so they may be unreliable. More parameters will be added.
You can probe the logic value at any node. See the `print` command for details.