This is m68k-rtems-as.info, produced by makeinfo version 4.6 from
../.././../binutils-2.13.2.1/gas/doc/m68k-rtems-as.texinfo.

START-INFO-DIR-ENTRY
* As: (m68k-rtems-as).                     The GNU assembler.
* Gas: (m68k-rtems-as).                    The GNU assembler.
END-INFO-DIR-ENTRY

   This file documents the GNU Assembler "as".

   Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002
Free Software Foundation, Inc.

   Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.1 or
any later version published by the Free Software Foundation; with no
Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
Texts.  A copy of the license is included in the section entitled "GNU
Free Documentation License".


File: m68k-rtems-as.info,  Node: M68K-Opts,  Next: M68K-Syntax,  Up: M68K-Dependent

M680x0 Options
--------------

The Motorola 680x0 version of `as' has a few machine dependent options:

`-l'
     You can use the `-l' option to shorten the size of references to
     undefined symbols.  If you do not use the `-l' option, references
     to undefined symbols are wide enough for a full `long' (32 bits).
     (Since `as' cannot know where these symbols end up, `as' can only
     allocate space for the linker to fill in later.  Since `as' does
     not know how far away these symbols are, it allocates as much
     space as it can.)  If you use this option, the references are only
     one word wide (16 bits).  This may be useful if you want the
     object file to be as small as possible, and you know that the
     relevant symbols are always less than 17 bits away.

`--register-prefix-optional'
     For some configurations, especially those where the compiler
     normally does not prepend an underscore to the names of user
     variables, the assembler requires a `%' before any use of a
     register name.  This is intended to let the assembler distinguish
     between C variables and functions named `a0' through `a7', and so
     on.  The `%' is always accepted, but is not required for certain
     configurations, notably `sun3'.  The `--register-prefix-optional'
     option may be used to permit omitting the `%' even for
     configurations for which it is normally required.  If this is
     done, it will generally be impossible to refer to C variables and
     functions with the same names as register names.

`--bitwise-or'
     Normally the character `|' is treated as a comment character, which
     means that it can not be used in expressions.  The `--bitwise-or'
     option turns `|' into a normal character.  In this mode, you must
     either use C style comments, or start comments with a `#' character
     at the beginning of a line.

`--base-size-default-16  --base-size-default-32'
     If you use an addressing mode with a base register without
     specifying the size, `as' will normally use the full 32 bit value.
     For example, the addressing mode `%a0@(%d0)' is equivalent to
     `%a0@(%d0:l)'.  You may use the `--base-size-default-16' option to
     tell `as' to default to using the 16 bit value.  In this case,
     `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'.  You may use the
     `--base-size-default-32' option to restore the default behaviour.

`--disp-size-default-16  --disp-size-default-32'
     If you use an addressing mode with a displacement, and the value
     of the displacement is not known, `as' will normally assume that
     the value is 32 bits.  For example, if the symbol `disp' has not
     been defined, `as' will assemble the addressing mode
     `%a0@(disp,%d0)' as though `disp' is a 32 bit value.  You may use
     the `--disp-size-default-16' option to tell `as' to instead assume
     that the displacement is 16 bits.  In this case, `as' will
     assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value.  You
     may use the `--disp-size-default-32' option to restore the default
     behaviour.

`--pcrel'
     Always keep branches PC-relative.  In the M680x0 architecture all
     branches are defined as PC-relative.  However, on some processors
     they are limited to word displacements maximum.  When `as' needs a
     long branch that is not available, it normally emits an absolute
     jump instead.  This option disables this substitution.  When this
     option is given and no long branches are available, only word
     branches will be emitted.  An error message will be generated if a
     word branch cannot reach its target.  This option has no effect on
     68020 and other processors that have long branches.  *note Branch
     Improvement: M68K-Branch..

`-m68000'
     `as' can assemble code for several different members of the
     Motorola 680x0 family.  The default depends upon how `as' was
     configured when it was built; normally, the default is to assemble
     code for the 68020 microprocessor.  The following options may be
     used to change the default.  These options control which
     instructions and addressing modes are permitted.  The members of
     the 680x0 family are very similar.  For detailed information about
     the differences, see the Motorola manuals.

    `-m68000'
    `-m68ec000'
    `-m68hc000'
    `-m68hc001'
    `-m68008'
    `-m68302'
    `-m68306'
    `-m68307'
    `-m68322'
    `-m68356'
          Assemble for the 68000. `-m68008', `-m68302', and so on are
          synonyms for `-m68000', since the chips are the same from the
          point of view of the assembler.

    `-m68010'
          Assemble for the 68010.

    `-m68020'
    `-m68ec020'
          Assemble for the 68020.  This is normally the default.

    `-m68030'
    `-m68ec030'
          Assemble for the 68030.

    `-m68040'
    `-m68ec040'
          Assemble for the 68040.

    `-m68060'
    `-m68ec060'
          Assemble for the 68060.

    `-mcpu32'
    `-m68330'
    `-m68331'
    `-m68332'
    `-m68333'
    `-m68334'
    `-m68336'
    `-m68340'
    `-m68341'
    `-m68349'
    `-m68360'
          Assemble for the CPU32 family of chips.

    `-m5200'
          Assemble for the ColdFire family of chips.

    `-m68881'
    `-m68882'
          Assemble 68881 floating point instructions.  This is the
          default for the 68020, 68030, and the CPU32.  The 68040 and
          68060 always support floating point instructions.

    `-mno-68881'
          Do not assemble 68881 floating point instructions.  This is
          the default for 68000 and the 68010.  The 68040 and 68060
          always support floating point instructions, even if this
          option is used.

    `-m68851'
          Assemble 68851 MMU instructions.  This is the default for the
          68020, 68030, and 68060.  The 68040 accepts a somewhat
          different set of MMU instructions; `-m68851' and `-m68040'
          should not be used together.

    `-mno-68851'
          Do not assemble 68851 MMU instructions.  This is the default
          for the 68000, 68010, and the CPU32.  The 68040 accepts a
          somewhat different set of MMU instructions.


File: m68k-rtems-as.info,  Node: M68K-Syntax,  Next: M68K-Moto-Syntax,  Prev: M68K-Opts,  Up: M68K-Dependent

Syntax
------

This syntax for the Motorola 680x0 was developed at MIT.

   The 680x0 version of `as' uses instructions names and syntax
compatible with the Sun assembler.  Intervening periods are ignored;
for example, `movl' is equivalent to `mov.l'.

   In the following table APC stands for any of the address registers
(`%a0' through `%a7'), the program counter (`%pc'), the zero-address
relative to the program counter (`%zpc'), a suppressed address register
(`%za0' through `%za7'), or it may be omitted entirely.  The use of
SIZE means one of `w' or `l', and it may be omitted, along with the
leading colon, unless a scale is also specified.  The use of SCALE
means one of `1', `2', `4', or `8', and it may always be omitted along
with the leading colon.

   The following addressing modes are understood:
"Immediate"
     `#NUMBER'

"Data Register"
     `%d0' through `%d7'

"Address Register"
     `%a0' through `%a7'
     `%a7' is also known as `%sp', i.e. the Stack Pointer.  `%a6' is
     also known as `%fp', the Frame Pointer.

"Address Register Indirect"
     `%a0@' through `%a7@'

"Address Register Postincrement"
     `%a0@+' through `%a7@+'

"Address Register Predecrement"
     `%a0@-' through `%a7@-'

"Indirect Plus Offset"
     `APC@(NUMBER)'

"Index"
     `APC@(NUMBER,REGISTER:SIZE:SCALE)'

     The NUMBER may be omitted.

"Postindex"
     `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)'

     The ONUMBER or the REGISTER, but not both, may be omitted.

"Preindex"
     `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)'

     The NUMBER may be omitted.  Omitting the REGISTER produces the
     Postindex addressing mode.

"Absolute"
     `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'.


File: m68k-rtems-as.info,  Node: M68K-Moto-Syntax,  Next: M68K-Float,  Prev: M68K-Syntax,  Up: M68K-Dependent

Motorola Syntax
---------------

The standard Motorola syntax for this chip differs from the syntax
already discussed (*note Syntax: M68K-Syntax.).  `as' can accept
Motorola syntax for operands, even if MIT syntax is used for other
operands in the same instruction.  The two kinds of syntax are fully
compatible.

   In the following table APC stands for any of the address registers
(`%a0' through `%a7'), the program counter (`%pc'), the zero-address
relative to the program counter (`%zpc'), or a suppressed address
register (`%za0' through `%za7').  The use of SIZE means one of `w' or
`l', and it may always be omitted along with the leading dot.  The use
of SCALE means one of `1', `2', `4', or `8', and it may always be
omitted along with the leading asterisk.

   The following additional addressing modes are understood:

"Address Register Indirect"
     `(%a0)' through `(%a7)'
     `%a7' is also known as `%sp', i.e. the Stack Pointer.  `%a6' is
     also known as `%fp', the Frame Pointer.

"Address Register Postincrement"
     `(%a0)+' through `(%a7)+'

"Address Register Predecrement"
     `-(%a0)' through `-(%a7)'

"Indirect Plus Offset"
     `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'.

     The NUMBER may also appear within the parentheses, as in
     `(NUMBER,%A0)'.  When used with the PC, the NUMBER may be omitted
     (with an address register, omitting the NUMBER produces Address
     Register Indirect mode).

"Index"
     `NUMBER(APC,REGISTER.SIZE*SCALE)'

     The NUMBER may be omitted, or it may appear within the
     parentheses.  The APC may be omitted.  The REGISTER and the APC
     may appear in either order.  If both APC and REGISTER are address
     registers, and the SIZE and SCALE are omitted, then the first
     register is taken as the base register, and the second as the
     index register.

"Postindex"
     `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)'

     The ONUMBER, or the REGISTER, or both, may be omitted.  Either the
     NUMBER or the APC may be omitted, but not both.

"Preindex"
     `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)'

     The NUMBER, or the APC, or the REGISTER, or any two of them, may
     be omitted.  The ONUMBER may be omitted.  The REGISTER and the APC
     may appear in either order.  If both APC and REGISTER are address
     registers, and the SIZE and SCALE are omitted, then the first
     register is taken as the base register, and the second as the
     index register.


File: m68k-rtems-as.info,  Node: M68K-Float,  Next: M68K-Directives,  Prev: M68K-Moto-Syntax,  Up: M68K-Dependent

Floating Point
--------------

Packed decimal (P) format floating literals are not supported.  Feel
free to add the code!

   The floating point formats generated by directives are these.

`.float'
     `Single' precision floating point constants.

`.double'
     `Double' precision floating point constants.

`.extend'
`.ldouble'
     `Extended' precision (`long double') floating point constants.


File: m68k-rtems-as.info,  Node: M68K-Directives,  Next: M68K-opcodes,  Prev: M68K-Float,  Up: M68K-Dependent

680x0 Machine Directives
------------------------

In order to be compatible with the Sun assembler the 680x0 assembler
understands the following directives.

`.data1'
     This directive is identical to a `.data 1' directive.

`.data2'
     This directive is identical to a `.data 2' directive.

`.even'
     This directive is a special case of the `.align' directive; it
     aligns the output to an even byte boundary.

`.skip'
     This directive is identical to a `.space' directive.


File: m68k-rtems-as.info,  Node: M68K-opcodes,  Prev: M68K-Directives,  Up: M68K-Dependent

Opcodes
-------

* Menu:

* M68K-Branch::                 Branch Improvement
* M68K-Chars::                  Special Characters


File: m68k-rtems-as.info,  Node: M68K-Branch,  Next: M68K-Chars,  Up: M68K-opcodes

Branch Improvement
..................

Certain pseudo opcodes are permitted for branch instructions.  They
expand to the shortest branch instruction that reach the target.
Generally these mnemonics are made by substituting `j' for `b' at the
start of a Motorola mnemonic.

   The following table summarizes the pseudo-operations.  A `*' flags
cases that are more fully described after the table:

               Displacement
               +------------------------------------------------------------
               |                68020           68000/10, not PC-relative OK
     Pseudo-Op |BYTE    WORD    LONG            ABSOLUTE LONG JUMP    **
               +------------------------------------------------------------
          jbsr |bsrs    bsrw    bsrl            jsr
           jra |bras    braw    bral            jmp
     *     jXX |bXXs    bXXw    bXXl            bNXs;jmp
     *    dbXX | N/A    dbXXw   dbXX;bras;bral  dbXX;bras;jmp
          fjXX | N/A    fbXXw   fbXXl            N/A
     
     XX: condition
     NX: negative of condition XX
                       `*'--see full description below
         `**'--this expansion mode is disallowed by `--pcrel'
`jbsr'
`jra'
     These are the simplest jump pseudo-operations; they always map to
     one particular machine instruction, depending on the displacement
     to the branch target.  This instruction will be a byte or word
     branch is that is sufficient.  Otherwise, a long branch will be
     emitted if available.  If no long branches are available and the
     `--pcrel' option is not given, an absolute long jump will be
     emitted instead.  If no long branches are available, the `--pcrel'
     option is given, and a word branch cannot reach the target, an
     error message is generated.

     In addition to standard branch operands, `as' allows these
     pseudo-operations to have all operands that are allowed for jsr
     and jmp, substituting these instructions if the operand given is
     not valid for a branch instruction.

`jXX'
     Here, `jXX' stands for an entire family of pseudo-operations,
     where XX is a conditional branch or condition-code test.  The full
     list of pseudo-ops in this family is:
           jhi   jls   jcc   jcs   jne   jeq   jvc
           jvs   jpl   jmi   jge   jlt   jgt   jle

     Usually, each of these pseudo-operations expands to a single branch
     instruction.  However, if a word branch is not sufficient, no long
     branches are available, and the `--pcrel' option is not given, `as'
     issues a longer code fragment in terms of NX, the opposite
     condition to XX.  For example, under these conditions:
              jXX foo
     gives
               bNXs oof
               jmp foo
           oof:

`dbXX'
     The full family of pseudo-operations covered here is
           dbhi   dbls   dbcc   dbcs   dbne   dbeq   dbvc
           dbvs   dbpl   dbmi   dbge   dblt   dbgt   dble
           dbf    dbra   dbt

     Motorola `dbXX' instructions allow word displacements only.  When
     a word displacement is sufficient, each of these pseudo-operations
     expands to the corresponding Motorola instruction.  When a word
     displacement is not sufficient and long branches are available,
     when the source reads `dbXX foo', `as' emits
               dbXX oo1
               bras oo2
           oo1:bral foo
           oo2:

     If, however, long branches are not available and the `--pcrel'
     option is not given, `as' emits
               dbXX oo1
               bras oo2
           oo1:jmp foo
           oo2:

`fjXX'
     This family includes
           fjne   fjeq   fjge   fjlt   fjgt   fjle   fjf
           fjt    fjgl   fjgle  fjnge  fjngl  fjngle fjngt
           fjnle  fjnlt  fjoge  fjogl  fjogt  fjole  fjolt
           fjor   fjseq  fjsf   fjsne  fjst   fjueq  fjuge
           fjugt  fjule  fjult  fjun

     Each of these pseudo-operations always expands to a single Motorola
     coprocessor branch instruction, word or long.  All Motorola
     coprocessor branch instructions allow both word and long
     displacements.



File: m68k-rtems-as.info,  Node: M68K-Chars,  Prev: M68K-Branch,  Up: M68K-opcodes

Special Characters
..................

The immediate character is `#' for Sun compatibility.  The line-comment
character is `|' (unless the `--bitwise-or' option is used).  If a `#'
appears at the beginning of a line, it is treated as a comment unless
it looks like `# line file', in which case it is treated normally.


File: m68k-rtems-as.info,  Node: M68HC11-Dependent,  Next: M88K-Dependent,  Prev: M68K-Dependent,  Up: Machine Dependencies

M68HC11 and M68HC12 Dependent Features
======================================

* Menu:

* M68HC11-Opts::                   M68HC11 and M68HC12 Options
* M68HC11-Syntax::                 Syntax
* M68HC11-Float::                  Floating Point
* M68HC11-opcodes::                Opcodes


File: m68k-rtems-as.info,  Node: M68HC11-Opts,  Next: M68HC11-Syntax,  Up: M68HC11-Dependent

M68HC11 and M68HC12 Options
---------------------------

The Motorola 68HC11 and 68HC12 version of `as' has a few machine
dependent options.

   This option switches the assembler in the M68HC11 mode. In this mode,
the assembler only accepts 68HC11 operands and mnemonics. It produces
code for the 68HC11.

   This option switches the assembler in the M68HC12 mode. In this mode,
the assembler also accepts 68HC12 operands and mnemonics. It produces
code for the 68HC12. A fiew 68HC11 instructions are replaced by some
68HC12 instructions as recommended by Motorola specifications.

   You can use the `--strict-direct-mode' option to disable the
automatic translation of direct page mode addressing into extended mode
when the instruction does not support direct mode.  For example, the
`clr' instruction does not support direct page mode addressing. When it
is used with the direct page mode, `as' will ignore it and generate an
absolute addressing.  This option prevents `as' from doing this, and
the wrong usage of the direct page mode will raise an error.

   The `--short-branchs' option turns off the translation of relative
branches into absolute branches when the branch offset is out of range.
By default `as' transforms the relative branch (`bsr', `bgt', `bge',
`beq', `bne', `ble', `blt', `bhi', `bcc', `bls', `bcs', `bmi', `bvs',
`bvs', `bra') into an absolute branch when the offset is out of the
-128 .. 127 range.  In that case, the `bsr' instruction is translated
into a `jsr', the `bra' instruction is translated into a `jmp' and the
conditional branchs instructions are inverted and followed by a `jmp'.
This option disables these translations and `as' will generate an error
if a relative branch is out of range. This option does not affect the
optimization associated to the `jbra', `jbsr' and `jbXX' pseudo opcodes.

   The `--force-long-branchs' option forces the translation of relative
branches into absolute branches. This option does not affect the
optimization associated to the `jbra', `jbsr' and `jbXX' pseudo opcodes.

   You can use the `--print-insn-syntax' option to obtain the syntax
description of the instruction when an error is detected.

   The `--print-opcodes' option prints the list of all the instructions
with their syntax. The first item of each line represents the
instruction name and the rest of the line indicates the possible
operands for that instruction. The list is printed in alphabetical
order. Once the list is printed `as' exits.

   The `--generate-example' option is similar to `--print-opcodes' but
it generates an example for each instruction instead.


File: m68k-rtems-as.info,  Node: M68HC11-Syntax,  Next: M68HC11-Float,  Prev: M68HC11-Opts,  Up: M68HC11-Dependent

Syntax
------

In the M68HC11 syntax, the instruction name comes first and it may be
followed by one or several operands (up to three). Operands are
separated by comma (`,'). In the normal mode, `as' will complain if too
many operands are specified for a given instruction. In the MRI mode
(turned on with `-M' option), it will treat them as comments. Example:

     inx
     lda  #23
     bset 2,x #4
     brclr *bot #8 foo

   The following addressing modes are understood:
"Immediate"
     `#NUMBER'

"Address Register"
     `NUMBER,X', `NUMBER,Y'

     The NUMBER may be omitted in which case 0 is assumed.

"Direct Addressing mode"
     `*SYMBOL', or `*DIGITS'

"Absolute"
     `SYMBOL', or `DIGITS'


File: m68k-rtems-as.info,  Node: M68HC11-Float,  Next: M68HC11-opcodes,  Prev: M68HC11-Syntax,  Up: M68HC11-Dependent

Floating Point
--------------

Packed decimal (P) format floating literals are not supported.  Feel
free to add the code!

   The floating point formats generated by directives are these.

`.float'
     `Single' precision floating point constants.

`.double'
     `Double' precision floating point constants.

`.extend'
`.ldouble'
     `Extended' precision (`long double') floating point constants.


File: m68k-rtems-as.info,  Node: M68HC11-opcodes,  Prev: M68HC11-Float,  Up: M68HC11-Dependent

Opcodes
-------

* Menu:

* M68HC11-Branch::                 Branch Improvement


File: m68k-rtems-as.info,  Node: M68HC11-Branch,  Up: M68HC11-opcodes

Branch Improvement
..................

Certain pseudo opcodes are permitted for branch instructions.  They
expand to the shortest branch instruction that reach the target.
Generally these mnemonics are made by prepending `j' to the start of
Motorola mnemonic. These pseudo opcodes are not affected by the
`--short-branchs' or `--force-long-branchs' options.

   The following table summarizes the pseudo-operations.

                                   Displacement Width
               +-------------------------------------------------------------+
               |                     Options                                 |
               |    --short-branchs            --force-long-branchs          |
               +--------------------------+----------------------------------+
     Pseudo-Op |BYTE             WORD     | BYTE          WORD               |
               +--------------------------+----------------------------------+
           bsr | bsr <pc-rel>    <error>  |               jsr <abs>          |
           bra | bra <pc-rel>    <error>  |               jmp <abs>          |
          jbsr | bsr <pc-rel>   jsr <abs> | bsr <pc-rel>  jsr <abs>          |
          jbra | bra <pc-rel>   jmp <abs> | bra <pc-rel>  jmp <abs>          |
           bXX | bXX <pc-rel>    <error>  |               bNX +3; jmp <abs>  |
          jbXX | bXX <pc-rel>   bNX +3;   | bXX <pc-rel>  bNX +3; jmp <abs>  |
               |                jmp <abs> |                                  |
               +--------------------------+----------------------------------+
     XX: condition
     NX: negative of condition XX

`jbsr'
`jbra'
     These are the simplest jump pseudo-operations; they always map to
     one particular machine instruction, depending on the displacement
     to the branch target.

`jbXX'
     Here, `jbXX' stands for an entire family of pseudo-operations,
     where XX is a conditional branch or condition-code test.  The full
     list of pseudo-ops in this family is:
           jbcc   jbeq   jbge   jbgt   jbhi   jbvs   jbpl  jblo
           jbcs   jbne   jblt   jble   jbls   jbvc   jbmi

     For the cases of non-PC relative displacements and long
     displacements, `as' issues a longer code fragment in terms of NX,
     the opposite condition to XX.  For example, for the non-PC
     relative case:
              jbXX foo
     gives
               bNXs oof
               jmp foo
           oof:



File: m68k-rtems-as.info,  Node: M88K-Dependent,  Next: MIPS-Dependent,  Prev: M68HC11-Dependent,  Up: Machine Dependencies

Motorola M88K Dependent Features
================================

* Menu:

* M88K Directives::     M88K Machine Directives


File: m68k-rtems-as.info,  Node: M88K Directives,  Up: M88K-Dependent

M88K Machine Directives
-----------------------

The M88K version of the assembler supports the following machine
directives:

`.align'
     This directive aligns the section program counter on the next
     4-byte boundary.

`.dfloat EXPR'
     This assembles a double precision (64-bit) floating point constant.

`.ffloat EXPR'
     This assembles a single precision (32-bit) floating point constant.

`.half EXPR'
     This directive assembles a half-word (16-bit) constant.

`.word EXPR'
     This assembles a word (32-bit) constant.

`.string "STR"'
     This directive behaves like the standard `.ascii' directive for
     copying STR into the object file.  The string is not terminated
     with a null byte.

`.set SYMBOL, VALUE'
     This directive creates a symbol named SYMBOL which is an alias for
     another symbol (possibly not yet defined).  This should not be
     confused with the mnemonic `set', which is a legitimate M88K
     instruction.

`.def SYMBOL, VALUE'
     This directive is synonymous with `.set' and is presumably provided
     for compatibility with other M88K assemblers.

`.bss SYMBOL, LENGTH, ALIGN'
     Reserve LENGTH bytes in the bss section for a local SYMBOL,
     aligned to the power of two specified by ALIGN.  LENGTH and ALIGN
     must be positive absolute expressions.  This directive differs
     from `.lcomm' only in that it permits you to specify an alignment.
     *Note `.lcomm': Lcomm.



File: m68k-rtems-as.info,  Node: MIPS-Dependent,  Next: MMIX-Dependent,  Prev: M88K-Dependent,  Up: Machine Dependencies

MIPS Dependent Features
=======================

   GNU `as' for MIPS architectures supports several different MIPS
processors, and MIPS ISA levels I through V, MIPS32, and MIPS64.  For
information about the MIPS instruction set, see `MIPS RISC
Architecture', by Kane and Heindrich (Prentice-Hall).  For an overview
of MIPS assembly conventions, see "Appendix D: Assembly Language
Programming" in the same work.

* Menu:

* MIPS Opts::   	Assembler options
* MIPS Object:: 	ECOFF object code
* MIPS Stabs::  	Directives for debugging information
* MIPS ISA::    	Directives to override the ISA level
* MIPS autoextend::	Directives for extending MIPS 16 bit instructions
* MIPS insn::		Directive to mark data as an instruction
* MIPS option stack::	Directives to save and restore options
* MIPS ASE instruction generation overrides:: Directives to control
  			generation of MIPS ASE instructions


File: m68k-rtems-as.info,  Node: MIPS Opts,  Next: MIPS Object,  Up: MIPS-Dependent

Assembler options
-----------------

The MIPS configurations of GNU `as' support these special options:

`-G NUM'
     This option sets the largest size of an object that can be
     referenced implicitly with the `gp' register.  It is only accepted
     for targets that use ECOFF format.  The default value is 8.

`-EB'
`-EL'
     Any MIPS configuration of `as' can select big-endian or
     little-endian output at run time (unlike the other GNU development
     tools, which must be configured for one or the other).  Use `-EB'
     to select big-endian output, and `-EL' for little-endian.

`-mips1'
`-mips2'
`-mips3'
`-mips4'
`-mips5'
`-mips32'
`-mips64'
     Generate code for a particular MIPS Instruction Set Architecture
     level.  `-mips1' corresponds to the R2000 and R3000 processors,
     `-mips2' to the R6000 processor, `-mips3' to the R4000 processor,
     and `-mips4' to the R8000 and R10000 processors.  `-mips5',
     `-mips32', and `-mips64' correspond to generic MIPS V, MIPS32, and
     MIPS64 ISA processors, respectively.  You can also switch
     instruction sets during the assembly; see *Note Directives to
     override the ISA level: MIPS ISA.

`-mgp32'
`-mfp32'
     Some macros have different expansions for 32-bit and 64-bit
     registers.  The register sizes are normally inferred from the ISA
     and ABI, but these flags force a certain group of registers to be
     treated as 32 bits wide at all times.  `-mgp32' controls the size
     of general-purpose registers and `-mfp32' controls the size of
     floating-point registers.

     On some MIPS variants there is a 32-bit mode flag; when this flag
     is set, 64-bit instructions generate a trap.  Also, some 32-bit
     OSes only save the 32-bit registers on a context switch, so it is
     essential never to use the 64-bit registers.

`-mgp64'
     Assume that 64-bit general purpose registers are available.  This
     is provided in the interests of symmetry with -gp32.

`-mips16'
`-no-mips16'
     Generate code for the MIPS 16 processor.  This is equivalent to
     putting `.set mips16' at the start of the assembly file.
     `-no-mips16' turns off this option.

`-mips3d'
`-no-mips3d'
     Generate code for the MIPS-3D Application Specific Extension.
     This tells the assembler to accept MIPS-3D instructions.
     `-no-mips3d' turns off this option.

`-mdmx'
`-no-mdmx'
     Generate code for the MDMX Application Specific Extension.  This
     tells the assembler to accept MDMX instructions.  `-no-mdmx' turns
     off this option.

`-mfix7000'
`-mno-fix7000'
     Cause nops to be inserted if the read of the destination register
     of an mfhi or mflo instruction occurs in the following two
     instructions.

`-m4010'
`-no-m4010'
     Generate code for the LSI R4010 chip.  This tells the assembler to
     accept the R4010 specific instructions (`addciu', `ffc', etc.),
     and to not schedule `nop' instructions around accesses to the `HI'
     and `LO' registers.  `-no-m4010' turns off this option.

`-m4650'
`-no-m4650'
     Generate code for the MIPS R4650 chip.  This tells the assembler
     to accept the `mad' and `madu' instruction, and to not schedule
     `nop' instructions around accesses to the `HI' and `LO' registers.
     `-no-m4650' turns off this option.

`-m3900'
`-no-m3900'
`-m4100'
`-no-m4100'
     For each option `-mNNNN', generate code for the MIPS RNNNN chip.
     This tells the assembler to accept instructions specific to that
     chip, and to schedule for that chip's hazards.

`-march=CPU'
     Generate code for a particular MIPS cpu.  It is exactly equivalent
     to `-mCPU', except that there are more value of CPU understood.
     Valid CPU value are:

          2000, 3000, 3900, 4000, 4010, 4100, 4111, 4300, 4400, 4600,
          4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, 6000,
          rm7000, 8000, 10000, 12000, mips32-4k, sb1

`-mtune=CPU'
     Schedule and tune for a particular MIPS cpu.  Valid CPU values are
     identical to `-march=CPU'.

`-mcpu=CPU'
     Generate code and schedule for a particular MIPS cpu.  This is
     exactly equivalent to `-march=CPU' and `-mtune=CPU'.  Valid CPU
     values are identical to `-march=CPU'.  Use of this option is
     discouraged.

`-nocpp'
     This option is ignored.  It is accepted for command-line
     compatibility with other assemblers, which use it to turn off C
     style preprocessing.  With GNU `as', there is no need for
     `-nocpp', because the GNU assembler itself never runs the C
     preprocessor.

`--construct-floats'
`--no-construct-floats'
     The `--no-construct-floats' option disables the construction of
     double width floating point constants by loading the two halves of
     the value into the two single width floating point registers that
     make up the double width register.  This feature is useful if the
     processor support the FR bit in its status  register, and this bit
     is known (by the programmer) to be set.  This bit prevents the
     aliasing of the double width register by the single width
     registers.

     By default `--construct-floats' is selected, allowing construction
     of these floating point constants.

`--trap'
`--no-break'
     `as' automatically macro expands certain division and
     multiplication instructions to check for overflow and division by
     zero.  This option causes `as' to generate code to take a trap
     exception rather than a break exception when an error is detected.
     The trap instructions are only supported at Instruction Set
     Architecture level 2 and higher.

`--break'
`--no-trap'
     Generate code to take a break exception rather than a trap
     exception when an error is detected.  This is the default.

`-n'
     When this option is used, `as' will issue a warning every time it
     generates a nop instruction from a macro.


File: m68k-rtems-as.info,  Node: MIPS Object,  Next: MIPS Stabs,  Prev: MIPS Opts,  Up: MIPS-Dependent

MIPS ECOFF object code
----------------------

Assembling for a MIPS ECOFF target supports some additional sections
besides the usual `.text', `.data' and `.bss'.  The additional sections
are `.rdata', used for read-only data, `.sdata', used for small data,
and `.sbss', used for small common objects.

   When assembling for ECOFF, the assembler uses the `$gp' (`$28')
register to form the address of a "small object".  Any object in the
`.sdata' or `.sbss' sections is considered "small" in this sense.  For
external objects, or for objects in the `.bss' section, you can use the
`gcc' `-G' option to control the size of objects addressed via `$gp';
the default value is 8, meaning that a reference to any object eight
bytes or smaller uses `$gp'.  Passing `-G 0' to `as' prevents it from
using the `$gp' register on the basis of object size (but the assembler
uses `$gp' for objects in `.sdata' or `sbss' in any case).  The size of
an object in the `.bss' section is set by the `.comm' or `.lcomm'
directive that defines it.  The size of an external object may be set
with the `.extern' directive.  For example, `.extern sym,4' declares
that the object at `sym' is 4 bytes in length, whie leaving `sym'
otherwise undefined.

   Using small ECOFF objects requires linker support, and assumes that
the `$gp' register is correctly initialized (normally done
automatically by the startup code).  MIPS ECOFF assembly code must not
modify the `$gp' register.


File: m68k-rtems-as.info,  Node: MIPS Stabs,  Next: MIPS ISA,  Prev: MIPS Object,  Up: MIPS-Dependent

Directives for debugging information
------------------------------------

MIPS ECOFF `as' supports several directives used for generating
debugging information which are not support by traditional MIPS
assemblers.  These are `.def', `.endef', `.dim', `.file', `.scl',
`.size', `.tag', `.type', `.val', `.stabd', `.stabn', and `.stabs'.
The debugging information generated by the three `.stab' directives can
only be read by GDB, not by traditional MIPS debuggers (this
enhancement is required to fully support C++ debugging).  These
directives are primarily used by compilers, not assembly language
programmers!


File: m68k-rtems-as.info,  Node: MIPS ISA,  Next: MIPS autoextend,  Prev: MIPS Stabs,  Up: MIPS-Dependent

Directives to override the ISA level
------------------------------------

GNU `as' supports an additional directive to change the MIPS
Instruction Set Architecture level on the fly: `.set mipsN'.  N should
be a number from 0 to 5, or 32 or 64.  The values 1 to 5, 32, and 64
make the assembler accept instructions for the corresponding ISA level,
from that point on in the assembly.  `.set mipsN' affects not only
which instructions are permitted, but also how certain macros are
expanded.  `.set mips0' restores the ISA level to its original level:
either the level you selected with command line options, or the default
for your configuration.  You can use this feature to permit specific
R4000 instructions while assembling in 32 bit mode.  Use this directive
with care!

   The directive `.set mips16' puts the assembler into MIPS 16 mode, in
which it will assemble instructions for the MIPS 16 processor.  Use
`.set nomips16' to return to normal 32 bit mode.

   Traditional MIPS assemblers do not support this directive.


File: m68k-rtems-as.info,  Node: MIPS autoextend,  Next: MIPS insn,  Prev: MIPS ISA,  Up: MIPS-Dependent

Directives for extending MIPS 16 bit instructions
-------------------------------------------------

By default, MIPS 16 instructions are automatically extended to 32 bits
when necessary.  The directive `.set noautoextend' will turn this off.
When `.set noautoextend' is in effect, any 32 bit instruction must be
explicitly extended with the `.e' modifier (e.g., `li.e $4,1000').  The
directive `.set autoextend' may be used to once again automatically
extend instructions when necessary.

   This directive is only meaningful when in MIPS 16 mode.  Traditional
MIPS assemblers do not support this directive.


File: m68k-rtems-as.info,  Node: MIPS insn,  Next: MIPS option stack,  Prev: MIPS autoextend,  Up: MIPS-Dependent

Directive to mark data as an instruction
----------------------------------------

The `.insn' directive tells `as' that the following data is actually
instructions.  This makes a difference in MIPS 16 mode: when loading
the address of a label which precedes instructions, `as' automatically
adds 1 to the value, so that jumping to the loaded address will do the
right thing.


File: m68k-rtems-as.info,  Node: MIPS option stack,  Next: MIPS ASE instruction generation overrides,  Prev: MIPS insn,  Up: MIPS-Dependent

Directives to save and restore options
--------------------------------------

The directives `.set push' and `.set pop' may be used to save and
restore the current settings for all the options which are controlled
by `.set'.  The `.set push' directive saves the current settings on a
stack.  The `.set pop' directive pops the stack and restores the
settings.

   These directives can be useful inside an macro which must change an
option such as the ISA level or instruction reordering but does not want
to change the state of the code which invoked the macro.

   Traditional MIPS assemblers do not support these directives.


File: m68k-rtems-as.info,  Node: MIPS ASE instruction generation overrides,  Prev: MIPS option stack,  Up: MIPS-Dependent

Directives to control generation of MIPS ASE instructions
---------------------------------------------------------

The directive `.set mips3d' makes the assembler accept instructions
from the MIPS-3D Application Specific Extension from that point on in
the assembly.  The `.set nomips3d' directive prevents MIPS-3D
instructions from being accepted.

   The directive `.set mdmx' makes the assembler accept instructions
from the MDMX Application Specific Extension from that point on in the
assembly.  The `.set nomdmx' directive prevents MDMX instructions from
being accepted.

   Traditional MIPS assemblers do not support these directives.


File: m68k-rtems-as.info,  Node: MMIX-Dependent,  Next: SH-Dependent,  Prev: MIPS-Dependent,  Up: Machine Dependencies

MMIX Dependent Features
=======================

* Menu:

* MMIX-Opts::              Command-line Options
* MMIX-Expand::            Instruction expansion
* MMIX-Syntax::            Syntax
* MMIX-mmixal::		   Differences to `mmixal' syntax and semantics


File: m68k-rtems-as.info,  Node: MMIX-Opts,  Next: MMIX-Expand,  Up: MMIX-Dependent

Command-line Options
--------------------

The MMIX version of `as' has some machine-dependent options.

   When `--fixed-special-register-names' is specified, only the register
names specified in *Note MMIX-Regs:: are recognized in the instructions
`PUT' and `GET'.

   You can use the `--globalize-symbols' to make all symbols global.
This option is useful when splitting up a `mmixal' program into several
files.

   The `--gnu-syntax' turns off most syntax compatibility with
`mmixal'.  Its usability is currently doubtful.

   The `--relax' option is not fully supported, but will eventually make
the object file prepared for linker relaxation.

   If you want to avoid inadvertently calling a predefined symbol and
would rather get an error, for example when using `as' with a compiler
or other machine-generated code, specify `--no-predefined-syms'.  This
turns off built-in predefined definitions of all such symbols,
including rounding-mode symbols, segment symbols, `BIT' symbols, and
`TRAP' symbols used in `mmix' "system calls".  It also turns off
predefined special-register names, except when used in `PUT' and `GET'
instructions.

   By default, some instructions are expanded to fit the size of the
operand or an external symbol (*note MMIX-Expand::).  By passing
`--no-expand', no such expansion will be done, instead causing errors
at link time if the operand does not fit.

   The `mmixal' documentation (*note mmixsite::) specifies that global
registers allocated with the `GREG' directive (*note MMIX-greg::) and
initialized to the same non-zero value, will refer to the same global
register.  This isn't strictly enforcable in `as' since the final
addresses aren't known until link-time, but it will do an effort unless
the `--no-merge-gregs' option is specified.  (Register merging isn't
yet implemented in `ld'.)

   `as' will warn every time it expands an instruction to fit an
operand unless the option `-x' is specified.  It is believed that this
behaviour is more useful than just mimicking `mmixal''s behaviour, in
which instructions are only expanded if the `-x' option is specified,
and assembly fails otherwise, when an instruction needs to be expanded.
It needs to be kept in mind that `mmixal' is both an assembler and
linker, while `as' will expand instructions that at link stage can be
contracted.  (Though linker relaxation isn't yet implemented in `ld'.)
The option `-x' also imples `--linker-allocated-gregs'.

   Usually a two-operand-expression (*note GREG-base::) without a
matching `GREG' directive is treated as an error by `as'.  When the
option `--linker-allocated-gregs' is in effect, they are instead passed
through to the linker, which will allocate as many global registers as
is needed.


File: m68k-rtems-as.info,  Node: MMIX-Expand,  Next: MMIX-Syntax,  Prev: MMIX-Opts,  Up: MMIX-Dependent

Instruction expansion
---------------------

When `as' encounters an instruction with an operand that is either not
known or does not fit the operand size of the instruction, `as' (and
`ld') will expand the instruction into a sequence of instructions
semantically equivalent to the operand fitting the instruction.
Expansion will take place for the following instructions:

`GETA'
     Expands to a sequence of four instructions: `SETL', `INCML',
     `INCMH' and `INCH'.  The operand must be a multiple of four.

Conditional branches
     A branch instruction is turned into a branch with the complemented
     condition and prediction bit over five instructions; four
     instructions setting `$255' to the operand value, which like with
     `GETA' must be a multiple of four, and a final `GO $255,$255,0'.

`PUSHJ'
     Similar to expansion for conditional branches; four instructions
     set `$255' to the operand value, followed by a `PUSHGO
     $255,$255,0'.

`JMP'
     Similar to conditional branches and `PUSHJ'.  The final instruction
     is `GO $255,$255,0'.

   The linker `ld' is expected to shrink these expansions for code
assembled with `--relax' (though not currently implemented).


File: m68k-rtems-as.info,  Node: MMIX-Syntax,  Next: MMIX-mmixal,  Prev: MMIX-Expand,  Up: MMIX-Dependent

Syntax
------

The assembly syntax is supposed to be upward compatible with that
described in Sections 1.3 and 1.4 of `The Art of Computer Programming,
Volume 1'.  Draft versions of those chapters as well as other MMIX
information is located at
<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>.  Most code
examples from the mmixal package located there should work unmodified
when assembled and linked as single files, with a few noteworthy
exceptions (*note MMIX-mmixal::).

   Before an instruction is emitted, the current location is aligned to
the next four-byte boundary.  If a label is defined at the beginning of
the line, its value will be the aligned value.

   In addition to the traditional hex-prefix `0x', a hexadecimal number
can also be specified by the prefix character `#'.

   After all operands to an MMIX instruction or directive have been
specified, the rest of the line is ignored, treated as a comment.

* Menu:

* MMIX-Chars::		        Special Characters
* MMIX-Symbols::		Symbols
* MMIX-Regs::			Register Names
* MMIX-Pseudos::		Assembler Directives


File: m68k-rtems-as.info,  Node: MMIX-Chars,  Next: MMIX-Symbols,  Up: MMIX-Syntax

Special Characters
..................

The characters `*' and `#' are line comment characters; each start a
comment at the beginning of a line, but only at the beginning of a
line.  A `#' prefixes a hexadecimal number if found elsewhere on a line.

   Two other characters, `%' and `!', each start a comment anywhere on
the line.  Thus you can't use the `modulus' and `not' operators in
expressions normally associated with these two characters.

   A `;' is a line separator, treated as a new-line, so separate
instructions can be specified on a single line.


File: m68k-rtems-as.info,  Node: MMIX-Symbols,  Next: MMIX-Regs,  Prev: MMIX-Chars,  Up: MMIX-Syntax

Symbols
.......

The character `:' is permitted in identifiers.  There are two
exceptions to it being treated as any other symbol character: if a
symbol begins with `:', it means that the symbol is in the global
namespace and that the current prefix should not be prepended to that
symbol (*note MMIX-prefix::).  The `:' is then not considered part of
the symbol.  For a symbol in the label position (first on a line), a `:'
at the end of a symbol is silently stripped off.  A label is permitted,
but not required, to be followed by a `:', as with many other assembly
formats.

   The character `@' in an expression, is a synonym for `.', the
current location.

   In addition to the common forward and backward local symbol formats
(*note Symbol Names::), they can be specified with upper-case `B' and
`F', as in `8B' and `9F'.  A local label defined for the current
position is written with a `H' appended to the number:
     3H LDB $0,$1,2
   This and traditional local-label formats cannot be mixed: a label
must be defined and referred to using the same format.

   There's a minor caveat: just as for the ordinary local symbols, the
local symbols are translated into ordinary symbols using control
characters are to hide the ordinal number of the symbol.
Unfortunately, these symbols are not translated back in error messages.
Thus you may see confusing error messages when local symbols are used.
Control characters `\003' (control-C) and `\004' (control-D) are used
for the MMIX-specific local-symbol syntax.

   The symbol `Main' is handled specially; it is always global.

   By defining the symbols `__.MMIX.start..text' and
`__.MMIX.start..data', the address of respectively the `.text' and
`.data' segments of the final program can be defined, though when
linking more than one object file, the code or data in the object file
containing the symbol is not guaranteed to be start at that position;
just the final executable.  *Note MMIX-loc::.


File: m68k-rtems-as.info,  Node: MMIX-Regs,  Next: MMIX-Pseudos,  Prev: MMIX-Symbols,  Up: MMIX-Syntax

Register names
..............

Local and global registers are specified as `$0' to `$255'.  The
recognized special register names are `rJ', `rA', `rB', `rC', `rD',
`rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ',
`rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT',
`rWW', `rXX', `rYY' and `rZZ'.  A leading `:' is optional for special
register names.

   Local and global symbols can be equated to register names and used in
place of ordinary registers.

   Similarly for special registers, local and global symbols can be
used.  Also, symbols equated from numbers and constant expressions are
allowed in place of a special register, except when either of the
options `--no-predefined-syms' and `--fixed-special-register-names' are
specified.  Then only the special register names above are allowed for
the instructions having a special register operand; `GET' and `PUT'.


File: m68k-rtems-as.info,  Node: MMIX-Pseudos,  Prev: MMIX-Regs,  Up: MMIX-Syntax

Assembler Directives
....................

`LOC'
     The `LOC' directive sets the current location to the value of the
     operand field, which may include changing sections.  If the
     operand is a constant, the section is set to either `.data' if the
     value is `0x2000000000000000' or larger, else it is set to `.text'.
     Within a section, the current location may only be changed to
     monotonically higher addresses.  A LOC expression must be a
     previously defined symbol or a "pure" constant.

     An example, which sets the label PREV to the current location, and
     updates the current location to eight bytes forward:
          prev LOC @+8

     When a LOC has a constant as its operand, a symbol
     `__.MMIX.start..text' or `__.MMIX.start..data' is defined
     depending on the address as mentioned above.  Each such symbol is
     interpreted as special by the linker, locating the section at that
     address.  Note that if multiple files are linked, the first object
     file with that section will be mapped to that address (not
     necessarily the file with the LOC definition).

`LOCAL'
     Example:
           LOCAL external_symbol
           LOCAL 42
           .local asymbol

     This directive-operation generates a link-time assertion that the
     operand does not correspond to a global register.  The operand is
     an expression that at link-time resolves to a register symbol or a
     number.  A number is treated as the register having that number.
     There is one restriction on the use of this directive: the
     pseudo-directive must be placed in a section with contents, code
     or data.

`IS'
     The `IS' directive:
          asymbol IS an_expression
     sets the symbol `asymbol' to `an_expression'.  A symbol may not be
     set more than once using this directive.  Local labels may be set
     using this directive, for example:
          5H IS @+4

`GREG'
     This directive reserves a global register, gives it an initial
     value and optionally gives it a symbolic name.  Some examples:

          areg GREG
          breg GREG data_value
               GREG data_buffer
               .greg creg, another_data_value

     The symbolic register name can be used in place of a (non-special)
     register.  If a value isn't provided, it defaults to zero.  Unless
     the option `--no-merge-gregs' is specified, non-zero registers
     allocated with this directive may be eliminated by `as'; another
     register with the same value used in its place.  Any of the
     instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU',
     `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW',
     `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT',
     `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can
     have a value nearby an initial value in place of its second and
     third operands.  Here, "nearby" is defined as within the range
     0...255 from the initial value of such an allocated register.

          buffer1 BYTE 0,0,0,0,0
          buffer2 BYTE 0,0,0,0,0
           ...
           GREG buffer1
           LDOU $42,buffer2
     In the example above, the `Y' field of the `LDOUI' instruction
     (LDOU with a constant Z) will be replaced with the global register
     allocated for `buffer1', and the `Z' field will have the value 5,
     the offset from `buffer1' to `buffer2'.  The result is equivalent
     to this code:
          buffer1 BYTE 0,0,0,0,0
          buffer2 BYTE 0,0,0,0,0
           ...
          tmpreg GREG buffer1
           LDOU $42,tmpreg,(buffer2-buffer1)

     Global registers allocated with this directive are allocated in
     order higher-to-lower within a file.  Other than that, the exact
     order of register allocation and elimination is undefined.  For
     example, the order is undefined when more than one file with such
     directives are linked together.  With the options `-x' and
     `--linker-allocated-gregs', `GREG' directives for two-operand
     cases like the one mentioned above can be omitted.  Sufficient
     global registers will then be allocated by the linker.

`BYTE'
     The `BYTE' directive takes a series of operands separated by a
     comma.  If an operand is a string (*note Strings::), each
     character of that string is emitted as a byte.  Other operands
     must be constant expressions without forward references, in the
     range 0...255.  If you need operands having expressions with
     forward references, use `.byte' (*note Byte::).  An operand can be
     omitted, defaulting to a zero value.

`WYDE'
`TETRA'
`OCTA'
     The directives `WYDE', `TETRA' and `OCTA' emit constants of two,
     four and eight bytes size respectively.  Before anything else
     happens for the directive, the current location is aligned to the
     respective constant-size bondary.  If a label is defined at the
     beginning of the line, its value will be that after the alignment.
     A single operand can be omitted, defaulting to a zero value
     emitted for the directive.  Operands can be expressed as strings
     (*note Strings::), in which case each character in the string is
     emitted as a separate constant of the size indicated by the
     directive.

`PREFIX'
     The `PREFIX' directive sets a symbol name prefix to be prepended to
     all symbols (except local symbols, *note MMIX-Symbols::), that are
     not prefixed with `:', until the next `PREFIX' directive.  Such
     prefixes accumulate.  For example,
           PREFIX a
           PREFIX b
          c IS 0
     defines a symbol `abc' with the value 0.

`BSPEC'
`ESPEC'
     A pair of `BSPEC' and `ESPEC' directives delimit a section of
     special contents (without specified semantics).  Example:
           BSPEC 42
           TETRA 1,2,3
           ESPEC
     The single operand to `BSPEC' must be number in the range 0...255.
     The `BSPEC' number 80 is used by the GNU binutils implementation.


File: m68k-rtems-as.info,  Node: MMIX-mmixal,  Prev: MMIX-Syntax,  Up: MMIX-Dependent

Differences to `mmixal'
-----------------------

The binutils `as' and `ld' combination has a few differences in
function compared to `mmixal' (*note mmixsite::).

   The replacement of a symbol with a GREG-allocated register (*note
GREG-base::) is not handled the exactly same way in `as' as in
`mmixal'.  This is apparent in the `mmixal' example file `inout.mms',
where different registers with different offsets, eventually yielding
the same address, are used in the first instruction.  This type of
difference should however not affect the function of any program unless
it has specific assumptions about the allocated register number.

   Line numbers (in the `mmo' object format) are currently not
supported.

   Expression operator precedence is not that of mmixal: operator
precedence is that of the C programming language.  It's recommended to
use parentheses to explicitly specify wanted operator precedence
whenever more than one type of operators are used.

   The serialize unary operator `&', the fractional division operator
`//', the logical not operator `!' and the modulus operator `%' are not
available.

   Symbols are not global by default, unless the option
`--globalize-symbols' is passed.  Use the `.global' directive to
globalize symbols (*note Global::).

   Operand syntax is a bit stricter with `as' than `mmixal'.  For
example, you can't say `addu 1,2,3', instead you must write `addu
$1,$2,3'.

   You can't LOC to a lower address than those already visited (i.e.
"backwards").

   A LOC directive must come before any emitted code.

   Predefined symbols are visible as file-local symbols after use.  (In
the ELF file, that is--the linked mmo file has no notion of a file-local
symbol.)

   Some mapping of constant expressions to sections in LOC expressions
is attempted, but that functionality is easily confused and should be
avoided unless compatibility with `mmixal' is required.  A LOC
expression to `0x2000000000000000' or higher, maps to the `.data'
section and lower addresses map to the `.text' section (*note
MMIX-loc::).

   The code and data areas are each contiguous.  Sparse programs with
far-away LOC directives will take up the same amount of space as a
contiguous program with zeros filled in the gaps between the LOC
directives.  If you need sparse programs, you might try and get the
wanted effect with a linker script and splitting up the code parts into
sections (*note Section::).  Assembly code for this, to be compatible
with `mmixal', would look something like:
      .if 0
      LOC away_expression
      .else
      .section away,"ax"
      .fi
   `as' will not execute the LOC directive and `mmixal' ignores the
lines with `.'.  This construct can be used generally to help
compatibility.

   Symbols can't be defined twice-not even to the same value.

   Instruction mnemonics are recognized case-insensitive, though the
`IS' and `GREG' pseudo-operations must be specified in upper-case
characters.

   There's no unicode support.

   The following is a list of programs in `mmix.tar.gz', available at
<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>, last
checked with the version dated 2001-08-25 (md5sum
c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do
not assemble with `as':

`silly.mms'
     LOC to a previous address.

`sim.mms'
     Redefines symbol `Done'.

`test.mms'
     Uses the serial operator `&'.


File: m68k-rtems-as.info,  Node: PDP-11-Dependent,  Next: PJ-Dependent,  Prev: SH64-Dependent,  Up: Machine Dependencies

PDP-11 Dependent Features
=========================

* Menu:

* PDP-11-Options::		Options
* PDP-11-Pseudos::		Assembler Directives
* PDP-11-Syntax::		DEC Syntax versus BSD Syntax
* PDP-11-Mnemonics::		Instruction Naming
* PDP-11-Synthetic::		Synthetic Instructions


File: m68k-rtems-as.info,  Node: PDP-11-Options,  Next: PDP-11-Pseudos,  Up: PDP-11-Dependent

Options
-------

The PDP-11 version of `as' has a rich set of machine dependent options.

Code Generation Options
.......................

`-mpic | -mno-pic'
     Generate position-independent (or position-dependent) code.

     The default is to generate position-independent code.

Instruction Set Extention Options
.................................

These options enables or disables the use of extensions over the base
line instruction set as introduced by the first PDP-11 CPU: the KA11.
Most options come in two variants: a `-m'EXTENSION that enables
EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION.

   The default is to enable all extensions.

`-mall | -mall-extensions'
     Enable all instruction set extensions.

`-mno-extensions'
     Disable all instruction set extensions.

`-mcis | -mno-cis'
     Enable (or disable) the use of the commersial instruction set,
     which consists of these instructions: `ADDNI', `ADDN', `ADDPI',
     `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC',
     `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI',
     `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL',
     `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI',
     `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC',
     `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI',
     `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'.

`-mcsm | -mno-csm'
     Enable (or disable) the use of the `CSM' instruction.

`-meis | -mno-eis'
     Enable (or disable) the use of the extended instruction set, which
     consists of these instructions: `ASHC', `ASH', `DIV', `MARK',
     `MUL', `RTT', `SOB' `SXT', and `XOR'.

`-mfis | -mkev11'
`-mno-fis | -mno-kev11'
     Enable (or diasble) the use of the KEV11 floating-point
     instructions: `FADD', `FDIV', `FMUL', and `FSUB'.

`-mfpp | -mfpu | -mfp-11'
`-mno-fpp | -mno-fpu | -mno-fp-11'
     Enable (or disable) the use of FP-11 floating-point instructions:
     `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF',
     `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF',
     `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST',
     `SUBF', and `TSTF'.

`-mlimited-eis | -mno-limited-eis'
     Enable (or disable) the use of the limited extended instruction
     set: `MARK', `RTT', `SOB', `SXT', and `XOR'.

     The -mno-limited-eis options also implies -mno-eis.

`-mmfpt | -mno-mfpt'
     Enable (or disable) the use of the `MFPT' instruction.

`-mmultiproc | -mno-multiproc'
     Enable (or disable) the use of multiprocessor instructions:
     `TSTSET' and `WRTLCK'.

`-mmxps | -mno-mxps'
     Enable (or disable) the use of the `MFPS' and `MTPS' instructions.

`-mspl | -mno-spl'
     Enable (or disable) the use of the `SPL' instruction.

     Enable (or disable) the use of the microcode instructions: `LDUB',
     `MED', and `XFC'.

CPU Model Options
.................

These options enable the instruction set extensions supported by a
particular CPU, and disables all other extensions.

`-mka11'
     KA11 CPU.  Base line instruction set only.

`-mkb11'
     KB11 CPU.  Enable extended instruction set and `SPL'.

`-mkd11a'
     KD11-A CPU.  Enable limited extended instruction set.

`-mkd11b'
     KD11-B CPU.  Base line instruction set only.

`-mkd11d'
     KD11-D CPU.  Base line instruction set only.

`-mkd11e'
     KD11-E CPU.  Enable extended instruction set, `MFPS', and `MTPS'.

`-mkd11f | -mkd11h | -mkd11q'
     KD11-F, KD11-H, or KD11-Q CPU.  Enable limited extended
     instruction set, `MFPS', and `MTPS'.

`-mkd11k'
     KD11-K CPU.  Enable extended instruction set, `LDUB', `MED',
     `MFPS', `MFPT', `MTPS', and `XFC'.

`-mkd11z'
     KD11-Z CPU.  Enable extended instruction set, `CSM', `MFPS',
     `MFPT', `MTPS', and `SPL'.

`-mf11'
     F11 CPU.  Enable extended instruction set, `MFPS', `MFPT', and
     `MTPS'.

`-mj11'
     J11 CPU.  Enable extended instruction set, `CSM', `MFPS', `MFPT',
     `MTPS', `SPL', `TSTSET', and `WRTLCK'.

`-mt11'
     T11 CPU.  Enable limited extended instruction set, `MFPS', and
     `MTPS'.

Machine Model Options
.....................

These options enable the instruction set extensions supported by a
particular machine model, and disables all other extensions.

`-m11/03'
     Same as `-mkd11f'.

`-m11/04'
     Same as `-mkd11d'.

`-m11/05 | -m11/10'
     Same as `-mkd11b'.

`-m11/15 | -m11/20'
     Same as `-mka11'.

`-m11/21'
     Same as `-mt11'.

`-m11/23 | -m11/24'
     Same as `-mf11'.

`-m11/34'
     Same as `-mkd11e'.

`-m11/34a'
     Ame as `-mkd11e' `-mfpp'.

`-m11/35 | -m11/40'
     Same as `-mkd11a'.

`-m11/44'
     Same as `-mkd11z'.

`-m11/45 | -m11/50 | -m11/55 | -m11/70'
     Same as `-mkb11'.

`-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94'
     Same as `-mj11'.

`-m11/60'
     Same as `-mkd11k'.


File: m68k-rtems-as.info,  Node: PDP-11-Pseudos,  Next: PDP-11-Syntax,  Prev: PDP-11-Options,  Up: PDP-11-Dependent

Assembler Directives
--------------------

The PDP-11 version of `as' has a few machine dependent assembler
directives.

`.bss'
     Switch to the `bss' section.

`.even'
     Align the location counter to an even number.


File: m68k-rtems-as.info,  Node: PDP-11-Syntax,  Next: PDP-11-Mnemonics,  Prev: PDP-11-Pseudos,  Up: PDP-11-Dependent

PDP-11 Assembly Language Syntax
-------------------------------

`as' supports both DEC syntax and BSD syntax.  The only difference is
that in DEC syntax, a `#' character is used to denote an immediate
constants, while in BSD syntax the character for this purpose is `$'.

   eneral-purpose registers are named `r0' through `r7'.  Mnemonic
alternatives for `r6' and `r7' are `sp' and `pc', respectively.

   Floating-point registers are named `ac0' through `ac3', or
alternatively `fr0' through `fr3'.

   Comments are started with a `#' or a `/' character, and extend to
the end of the line.  (FIXME: clash with immediates?)


File: m68k-rtems-as.info,  Node: PDP-11-Mnemonics,  Next: PDP-11-Synthetic,  Prev: PDP-11-Syntax,  Up: PDP-11-Dependent

Instruction Naming
------------------

Some instructions have alternative names.

`BCC'
     `BHIS'

`BCS'
     `BLO'

`L2DR'
     `L2D'

`L3DR'
     `L3D'

`SYS'
     `TRAP'


File: m68k-rtems-as.info,  Node: PDP-11-Synthetic,  Prev: PDP-11-Mnemonics,  Up: PDP-11-Dependent

Synthetic Instructions
----------------------

The `JBR' and `J'CC synthetic instructions are not supported yet.


File: m68k-rtems-as.info,  Node: PJ-Dependent,  Next: PPC-Dependent,  Prev: PDP-11-Dependent,  Up: Machine Dependencies

picoJava Dependent Features
===========================

* Menu:

* PJ Options::              Options


File: m68k-rtems-as.info,  Node: PJ Options,  Up: PJ-Dependent

Options
-------

`as' has two addiitional command-line options for the picoJava
architecture.
`-ml'
     This option selects little endian data output.

`-mb'
     This option selects big endian data output.


File: m68k-rtems-as.info,  Node: PPC-Dependent,  Next: Sparc-Dependent,  Prev: PJ-Dependent,  Up: Machine Dependencies

PowerPC Dependent Features
==========================

* Menu:

* PowerPC-Opts::                Options


File: m68k-rtems-as.info,  Node: PowerPC-Opts,  Up: PPC-Dependent

Options
-------

The PowerPC chip family includes several successive levels, using the
same core instruction set, but including a few additional instructions
at each level.  There are exceptions to this however.  For details on
what instructions each variant supports, please see the chip's
architecture reference manual.

   The following table lists all available PowerPC options.

`-mpwrx | -mpwr2'
     Generate code for POWER/2 (RIOS2).

`-mpwr'
     Generate code for POWER (RIOS1)

`-m601'
     Generate code for PowerPC 601.

`-mppc, -mppc32, -m603, -m604'
     Generate code for PowerPC 603/604.

`-m403, -m405'
     Generate code for PowerPC 403/405.

`-m7400, -m7410, -m7450, -m7455'
     Generate code for PowerPC 7400/7410/7450/7455.

`-mppc64, -m620'
     Generate code for PowerPC 620/625/630.

`-mppc64bridge'
     Generate code for PowerPC 64, including bridge insns.

`-mbooke64'
     Generate code for 64-bit BookE.

`-mbooke, mbooke32'
     Generate code for 32-bit BookE.

`-maltivec'
     Generate code for processors with AltiVec instructions.

`-mpower4'
     Generate code for Power4 architecture.

`-mcom'
     Generate code Power/PowerPC common instructions.

`-many'
     Generate code for any architecture (PWR/PWRX/PPC).

`-mregnames'
     Allow symbolic names for registers.

`-mno-regnames'
     Do not allow symbolic names for registers.

`-mrelocatable'
     Support for GCC's -mrelocatble option.

`-mrelocatable-lib'
     Support for GCC's -mrelocatble-lib option.

`-memb'
     Set PPC_EMB bit in ELF flags.

`-mlittle, -mlittle-endian'
     Generate code for a little endian machine.

`-mbig, -mbig-endian'
     Generate code for a big endian machine.

`-msolaris'
     Generate code for Solaris.

`-mno-solaris'
     Do not generate code for Solaris.


File: m68k-rtems-as.info,  Node: SH-Dependent,  Next: SH64-Dependent,  Prev: MMIX-Dependent,  Up: Machine Dependencies

Hitachi SH Dependent Features
=============================

* Menu:

* SH Options::              Options
* SH Syntax::               Syntax
* SH Floating Point::       Floating Point
* SH Directives::           SH Machine Directives
* SH Opcodes::              Opcodes


File: m68k-rtems-as.info,  Node: SH Options,  Next: SH Syntax,  Up: SH-Dependent

Options
-------

`as' has following command-line options for the Hitachi SH family.

`-little'
     Generate little endian code.

`-big'
     Generate big endian code.

`-relax'
     Alter jump instructions for long displacements.

`-small'
     Align sections to 4 byte boundaries, not 16.

`-dsp'
     Enable sh-dsp insns, and disable sh3e / sh4 insns.



File: m68k-rtems-as.info,  Node: SH Syntax,  Next: SH Floating Point,  Prev: SH Options,  Up: SH-Dependent

Syntax
------

* Menu:

* SH-Chars::                Special Characters
* SH-Regs::                 Register Names
* SH-Addressing::           Addressing Modes


File: m68k-rtems-as.info,  Node: SH-Chars,  Next: SH-Regs,  Up: SH Syntax

Special Characters
..................

`!' is the line comment character.

   You can use `;' instead of a newline to separate statements.

   Since `$' has no special meaning, you may use it in symbol names.


File: m68k-rtems-as.info,  Node: SH-Regs,  Next: SH-Addressing,  Prev: SH-Chars,  Up: SH Syntax

Register Names
..............

You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5',
`r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and `r15' to
refer to the SH registers.

   The SH also has these control registers:

`pr'
     procedure register (holds return address)

`pc'
     program counter

`mach'
`macl'
     high and low multiply accumulator registers

`sr'
     status register

`gbr'
     global base register

`vbr'
     vector base register (for interrupt vectors)


File: m68k-rtems-as.info,  Node: SH-Addressing,  Prev: SH-Regs,  Up: SH Syntax

Addressing Modes
................

`as' understands the following addressing modes for the SH.  `RN' in
the following refers to any of the numbered registers, but _not_ the
control registers.

`RN'
     Register direct

`@RN'
     Register indirect

`@-RN'
     Register indirect with pre-decrement

`@RN+'
     Register indirect with post-increment

`@(DISP, RN)'
     Register indirect with displacement

`@(R0, RN)'
     Register indexed

`@(DISP, GBR)'
     `GBR' offset

`@(R0, GBR)'
     GBR indexed

`ADDR'
`@(DISP, PC)'
     PC relative address (for branch or for addressing memory).  The
     `as' implementation allows you to use the simpler form ADDR
     anywhere a PC relative address is called for; the alternate form
     is supported for compatibility with other assemblers.

`#IMM'
     Immediate data


File: m68k-rtems-as.info,  Node: SH Floating Point,  Next: SH Directives,  Prev: SH Syntax,  Up: SH-Dependent

Floating Point
--------------

The SH family has no hardware floating point, but the `.float'
directive generates IEEE floating-point numbers for compatibility with
other development tools.


File: m68k-rtems-as.info,  Node: SH Directives,  Next: SH Opcodes,  Prev: SH Floating Point,  Up: SH-Dependent

SH Machine Directives
---------------------

`uaword'
`ualong'
     `as' will issue a warning when a misaligned `.word' or `.long'
     directive is used.  You may use `.uaword' or `.ualong' to indicate
     that the value is intentionally misaligned.


File: m68k-rtems-as.info,  Node: SH Opcodes,  Prev: SH Directives,  Up: SH-Dependent

Opcodes
-------

For detailed information on the SH machine instruction set, see
`SH-Microcomputer User's Manual' (Hitachi Micro Systems, Inc.).

   `as' implements all the standard SH opcodes.  No additional
pseudo-instructions are needed on this family.  Note, however, that
because `as' supports a simpler form of PC-relative addressing, you may
simply write (for example)

     mov.l  bar,r0

where other assemblers might require an explicit displacement to `bar'
from the program counter:

     mov.l  @(DISP, PC)

   Here is a summary of SH opcodes:

     Legend:
     Rn        a numbered register
     Rm        another numbered register
     #imm      immediate data
     disp      displacement
     disp8     8-bit displacement
     disp12    12-bit displacement
     
     add #imm,Rn                    lds.l @Rn+,PR
     add Rm,Rn                      mac.w @Rm+,@Rn+
     addc Rm,Rn                     mov #imm,Rn
     addv Rm,Rn                     mov Rm,Rn
     and #imm,R0                    mov.b Rm,@(R0,Rn)
     and Rm,Rn                      mov.b Rm,@-Rn
     and.b #imm,@(R0,GBR)           mov.b Rm,@Rn
     bf disp8                       mov.b @(disp,Rm),R0
     bra disp12                     mov.b @(disp,GBR),R0
     bsr disp12                     mov.b @(R0,Rm),Rn
     bt disp8                       mov.b @Rm+,Rn
     clrmac                         mov.b @Rm,Rn
     clrt                           mov.b R0,@(disp,Rm)
     cmp/eq #imm,R0                 mov.b R0,@(disp,GBR)
     cmp/eq Rm,Rn                   mov.l Rm,@(disp,Rn)
     cmp/ge Rm,Rn                   mov.l Rm,@(R0,Rn)
     cmp/gt Rm,Rn                   mov.l Rm,@-Rn
     cmp/hi Rm,Rn                   mov.l Rm,@Rn
     cmp/hs Rm,Rn                   mov.l @(disp,Rn),Rm
     cmp/pl Rn                      mov.l @(disp,GBR),R0
     cmp/pz Rn                      mov.l @(disp,PC),Rn
     cmp/str Rm,Rn                  mov.l @(R0,Rm),Rn
     div0s Rm,Rn                    mov.l @Rm+,Rn
     div0u                          mov.l @Rm,Rn
     div1 Rm,Rn                     mov.l R0,@(disp,GBR)
     exts.b Rm,Rn                   mov.w Rm,@(R0,Rn)
     exts.w Rm,Rn                   mov.w Rm,@-Rn
     extu.b Rm,Rn                   mov.w Rm,@Rn
     extu.w Rm,Rn                   mov.w @(disp,Rm),R0
     jmp @Rn                        mov.w @(disp,GBR),R0
     jsr @Rn                        mov.w @(disp,PC),Rn
     ldc Rn,GBR                     mov.w @(R0,Rm),Rn
     ldc Rn,SR                      mov.w @Rm+,Rn
     ldc Rn,VBR                     mov.w @Rm,Rn
     ldc.l @Rn+,GBR                 mov.w R0,@(disp,Rm)
     ldc.l @Rn+,SR                  mov.w R0,@(disp,GBR)
     ldc.l @Rn+,VBR                 mova @(disp,PC),R0
     lds Rn,MACH                    movt Rn
     lds Rn,MACL                    muls Rm,Rn
     lds Rn,PR                      mulu Rm,Rn
     lds.l @Rn+,MACH                neg Rm,Rn
     lds.l @Rn+,MACL                negc Rm,Rn
     
     nop                            stc VBR,Rn
     not Rm,Rn                      stc.l GBR,@-Rn
     or #imm,R0                     stc.l SR,@-Rn
     or Rm,Rn                       stc.l VBR,@-Rn
     or.b #imm,@(R0,GBR)            sts MACH,Rn
     rotcl Rn                       sts MACL,Rn
     rotcr Rn                       sts PR,Rn
     rotl Rn                        sts.l MACH,@-Rn
     rotr Rn                        sts.l MACL,@-Rn
     rte                            sts.l PR,@-Rn
     rts                            sub Rm,Rn
     sett                           subc Rm,Rn
     shal Rn                        subv Rm,Rn
     shar Rn                        swap.b Rm,Rn
     shll Rn                        swap.w Rm,Rn
     shll16 Rn                      tas.b @Rn
     shll2 Rn                       trapa #imm
     shll8 Rn                       tst #imm,R0
     shlr Rn                        tst Rm,Rn
     shlr16 Rn                      tst.b #imm,@(R0,GBR)
     shlr2 Rn                       xor #imm,R0
     shlr8 Rn                       xor Rm,Rn
     sleep                          xor.b #imm,@(R0,GBR)
     stc GBR,Rn                     xtrct Rm,Rn
     stc SR,Rn


File: m68k-rtems-as.info,  Node: SH64-Dependent,  Next: PDP-11-Dependent,  Prev: SH-Dependent,  Up: Machine Dependencies

Hitachi SH64 Dependent Features
===============================

* Menu:

* SH64 Options::              Options
* SH64 Syntax::               Syntax
* SH64 Directives::           SH64 Machine Directives
* SH64 Opcodes::              Opcodes


File: m68k-rtems-as.info,  Node: SH64 Options,  Next: SH64 Syntax,  Up: SH64-Dependent

Options
-------

`-isa=shmedia | -isa=shcompact'
     Specify the default instruction set.  `SHmedia' specifies the
     32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes
     compatible with previous SH families.  The default depends on the
     ABI selected; the default for the 64-bit ABI is SHmedia, and the
     default for the 32-bit ABI is SHcompact.  If neither the ABI nor
     the ISA is specified, the default is 32-bit SHcompact.

     Note that the `.mode' pseudo-op is not permitted if the ISA is not
     specified on the command line.

`-abi=32 | -abi=64'
     Specify the default ABI.  If the ISA is specified and the ABI is
     not, the default ABI depends on the ISA, with SHmedia defaulting
     to 64-bit and SHcompact defaulting to 32-bit.

     Note that the `.abi' pseudo-op is not permitted if the ABI is not
     specified on the command line.  When the ABI is specified on the
     command line, any `.abi' pseudo-ops in the source must match it.

`-shcompact-const-crange'
     Emit code-range descriptors for constants in SHcompact code
     sections.

`-no-mix'
     Disallow SHmedia code in the same section as constants and
     SHcompact code.

`-no-expand'
     Do not expand MOVI, PT, PTA or PTB instructions.

`-expand-pt32'
     With -abi=64, expand PT, PTA and PTB instructions to 32 bits only.



File: m68k-rtems-as.info,  Node: SH64 Syntax,  Next: SH64 Directives,  Prev: SH64 Options,  Up: SH64-Dependent

Syntax
------

* Menu:

* SH64-Chars::                Special Characters
* SH64-Regs::                 Register Names
* SH64-Addressing::           Addressing Modes


File: m68k-rtems-as.info,  Node: SH64-Chars,  Next: SH64-Regs,  Up: SH64 Syntax

Special Characters
..................

`!' is the line comment character.

   You can use `;' instead of a newline to separate statements.

   Since `$' has no special meaning, you may use it in symbol names.


File: m68k-rtems-as.info,  Node: SH64-Regs,  Next: SH64-Addressing,  Prev: SH64-Chars,  Up: SH64 Syntax

Register Names
..............

You can use the predefined symbols `r0' through `r63' to refer to the
SH64 general registers, `cr0' through `cr63' for control registers,
`tr0' through `tr7' for target address registers, `fr0' through `fr63'
for single-precision floating point registers, `dr0' through `dr62'
(even numbered registers only) for double-precision floating point
registers, `fv0' through `fv60' (multiples of four only) for
single-precision floating point vectors, `fp0' through `fp62' (even
numbered registers only) for single-precision floating point pairs,
`mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of
single-precision floating point registers, `pc' for the program
counter, and `fpscr' for the floating point status and control register.

   You can also refer to the control registers by the mnemonics `sr',
`ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc',
`resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'.


File: m68k-rtems-as.info,  Node: SH64-Addressing,  Prev: SH64-Regs,  Up: SH64 Syntax

Addressing Modes
................

SH64 operands consist of either a register or immediate value.  The
immediate value can be a constant or label reference (or portion of a
label reference), as in this example:

     	movi	4,r2
     	pt	function, tr4
     	movi	(function >> 16) & 65535,r0
     	shori	function & 65535, r0
     	ld.l	r0,4,r0

   Instruction label references can reference labels in either SHmedia
or SHcompact.  To differentiate between the two, labels in SHmedia
sections will always have the least significant bit set (i.e. they will
be odd), which SHcompact labels will have the least significant bit
reset (i.e. they will be even).  If you need to reference the actual
address of a label, you can use the `datalabel' modifier, as in this
example:

     	.long	function
     	.long	datalabel function

   In that example, the first longword may or may not have the least
significant bit set depending on whether the label is an SHmedia label
or an SHcompact label.  The second longword will be the actual address
of the label, regardless of what type of lable it is.


File: m68k-rtems-as.info,  Node: SH64 Directives,  Next: SH64 Opcodes,  Prev: SH64 Syntax,  Up: SH64-Dependent

SH64 Machine Directives
-----------------------

In addition to the SH directives, the SH64 provides the following
directives:

`.mode [shmedia|shcompact]'
`.isa [shmedia|shcompact]'
     Specify the ISA for the following instructions (the two directives
     are equivalent).  Note that programs such as `objdump' rely on
     symbolic labels to determine when such mode switches occur (by
     checking the least significant bit of the label's address), so
     such mode/isa changes should always be followed by a label (in
     practice, this is true anyway).  Note that you cannot use these
     directives if you didn't specify an ISA on the command line.

`.abi [32|64]'
     Specify the ABI for the following instructions.  Note that you
     cannot use this directive unless you specified an ABI on the
     command line, and the ABIs specified must match.

`.uaquad'
     Like .uaword and .ualong, this allows you to specify an
     intenionally unaligned quadword (64 bit word).



File: m68k-rtems-as.info,  Node: SH64 Opcodes,  Prev: SH64 Directives,  Up: SH64-Dependent

Opcodes
-------

For detailed information on the SH64 machine instruction set, see
`SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.).

   `as' implements all the standard SH64 opcodes.  In addition, the
following pseudo-opcodes may be expanded into one or more alternate
opcodes:

`movi'
     If the value doesn't fit into a standard `movi' opcode, `as' will
     replace the `movi' with a sequence of `movi' and `shori' opcodes.

`pt'
     This expands to a sequence of `movi' and `shori' opcode, followed
     by a `ptrel' opcode, or to a `pta' or `ptb' opcode, depending on
     the label referenced.



File: m68k-rtems-as.info,  Node: Sparc-Dependent,  Next: V850-Dependent,  Prev: PPC-Dependent,  Up: Machine Dependencies

SPARC Dependent Features
========================

* Menu:

* Sparc-Opts::                  Options
* Sparc-Aligned-Data::		Option to enforce aligned data
* Sparc-Float::                 Floating Point
* Sparc-Directives::            Sparc Machine Directives


File: m68k-rtems-as.info,  Node: Sparc-Opts,  Next: Sparc-Aligned-Data,  Up: Sparc-Dependent

Options
-------

The SPARC chip family includes several successive levels, using the same
core instruction set, but including a few additional instructions at
each level.  There are exceptions to this however.  For details on what
instructions each variant supports, please see the chip's architecture
reference manual.

   By default, `as' assumes the core instruction set (SPARC v6), but
"bumps" the architecture level as needed: it switches to successively
higher architectures as it encounters instructions that only exist in
the higher levels.

   If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump
passed sparclite by default, an option must be passed to enable the v9
instructions.

   GAS treats sparclite as being compatible with v8, unless an
architecture is explicitly requested.  SPARC v9 is always incompatible
with sparclite.

`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite'
`-Av8plus | -Av8plusa | -Av9 | -Av9a'
     Use one of the `-A' options to select one of the SPARC
     architectures explicitly.  If you select an architecture
     explicitly, `as' reports a fatal error if it encounters an
     instruction or feature requiring an incompatible or higher level.

     `-Av8plus' and `-Av8plusa' select a 32 bit environment.

     `-Av9' and `-Av9a' select a 64 bit environment and are not
     available unless GAS is explicitly configured with 64 bit
     environment support.

     `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with
     UltraSPARC extensions.

`-xarch=v8plus | -xarch=v8plusa'
     For compatibility with the Solaris v9 assembler.  These options are
     equivalent to -Av8plus and -Av8plusa, respectively.

`-bump'
     Warn whenever it is necessary to switch to another level.  If an
     architecture level is explicitly requested, GAS will not issue
     warnings until that level is reached, and will then bump the level
     as required (except between incompatible levels).

`-32 | -64'
     Select the word size, either 32 bits or 64 bits.  These options
     are only available with the ELF object file format, and require
     that the necessary BFD support has been included.


File: m68k-rtems-as.info,  Node: Sparc-Aligned-Data,  Next: Sparc-Float,  Prev: Sparc-Opts,  Up: Sparc-Dependent

Enforcing aligned data
----------------------

SPARC GAS normally permits data to be misaligned.  For example, it
permits the `.long' pseudo-op to be used on a byte boundary.  However,
the native SunOS and Solaris assemblers issue an error when they see
misaligned data.

   You can use the `--enforce-aligned-data' option to make SPARC GAS
also issue an error about misaligned data, just as the SunOS and Solaris
assemblers do.

   The `--enforce-aligned-data' option is not the default because gcc
issues misaligned data pseudo-ops when it initializes certain packed
data structures (structures defined using the `packed' attribute).  You
may have to assemble with GAS in order to initialize packed data
structures in your own code.


File: m68k-rtems-as.info,  Node: Sparc-Float,  Next: Sparc-Directives,  Prev: Sparc-Aligned-Data,  Up: Sparc-Dependent

Floating Point
--------------

The Sparc uses IEEE floating-point numbers.


File: m68k-rtems-as.info,  Node: Sparc-Directives,  Prev: Sparc-Float,  Up: Sparc-Dependent

Sparc Machine Directives
------------------------

The Sparc version of `as' supports the following additional machine
directives:

`.align'
     This must be followed by the desired alignment in bytes.

`.common'
     This must be followed by a symbol name, a positive number, and
     `"bss"'.  This behaves somewhat like `.comm', but the syntax is
     different.

`.half'
     This is functionally identical to `.short'.

`.nword'
     On the Sparc, the `.nword' directive produces native word sized
     value, ie. if assembling with -32 it is equivalent to `.word', if
     assembling with -64 it is equivalent to `.xword'.

`.proc'
     This directive is ignored.  Any text following it on the same line
     is also ignored.

`.register'
     This directive declares use of a global application or system
     register.  It must be followed by a register name %g2, %g3, %g6 or
     %g7, comma and the symbol name for that register.  If symbol name
     is `#scratch', it is a scratch register, if it is `#ignore', it
     just surpresses any errors about using undeclared global register,
     but does not emit any information about it into the object file.
     This can be useful e.g. if you save the register before use and
     restore it after.

`.reserve'
     This must be followed by a symbol name, a positive number, and
     `"bss"'.  This behaves somewhat like `.lcomm', but the syntax is
     different.

`.seg'
     This must be followed by `"text"', `"data"', or `"data1"'.  It
     behaves like `.text', `.data', or `.data 1'.

`.skip'
     This is functionally identical to the `.space' directive.

`.word'
     On the Sparc, the `.word' directive produces 32 bit values,
     instead of the 16 bit values it produces on many other machines.

`.xword'
     On the Sparc V9 processor, the `.xword' directive produces 64 bit
     values.


File: m68k-rtems-as.info,  Node: Z8000-Dependent,  Next: Vax-Dependent,  Prev: V850-Dependent,  Up: Machine Dependencies

Z8000 Dependent Features
========================

   The Z8000 as supports both members of the Z8000 family: the
unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with
24 bit addresses.

   When the assembler is in unsegmented mode (specified with the
`unsegm' directive), an address takes up one word (16 bit) sized
register.  When the assembler is in segmented mode (specified with the
`segm' directive), a 24-bit address takes up a long (32 bit) register.
*Note Assembler Directives for the Z8000: Z8000 Directives, for a list
of other Z8000 specific assembler directives.

* Menu:

* Z8000 Options::               No special command-line options for Z8000
* Z8000 Syntax::                Assembler syntax for the Z8000
* Z8000 Directives::            Special directives for the Z8000
* Z8000 Opcodes::               Opcodes


File: m68k-rtems-as.info,  Node: Z8000 Options,  Next: Z8000 Syntax,  Up: Z8000-Dependent

Options
-------

`as' has no additional command-line options for the Zilog Z8000 family.


File: m68k-rtems-as.info,  Node: Z8000 Syntax,  Next: Z8000 Directives,  Prev: Z8000 Options,  Up: Z8000-Dependent

Syntax
------

* Menu:

* Z8000-Chars::                Special Characters
* Z8000-Regs::                 Register Names
* Z8000-Addressing::           Addressing Modes


File: m68k-rtems-as.info,  Node: Z8000-Chars,  Next: Z8000-Regs,  Up: Z8000 Syntax

Special Characters
..................

`!' is the line comment character.

   You can use `;' instead of a newline to separate statements.


File: m68k-rtems-as.info,  Node: Z8000-Regs,  Next: Z8000-Addressing,  Prev: Z8000-Chars,  Up: Z8000 Syntax

Register Names
..............

The Z8000 has sixteen 16 bit registers, numbered 0 to 15.  You can refer
to different sized groups of registers by register number, with the
prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' for
64 bit registers.  You can also refer to the contents of the first
eight (of the sixteen 16 bit registers) by bytes.  They are named `rNh'
and `rNl'.

_byte registers_
     r0l r0h r1h r1l r2h r2l r3h r3l
     r4h r4l r5h r5l r6h r6l r7h r7l
     
_word registers_
     r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
     
_long word registers_
     rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
     
_quad word registers_
     rq0 rq4 rq8 rq12


File: m68k-rtems-as.info,  Node: Z8000-Addressing,  Prev: Z8000-Regs,  Up: Z8000 Syntax

Addressing Modes
................

as understands the following addressing modes for the Z8000:

`rN'
     Register direct

`@rN'
     Indirect register

`ADDR'
     Direct: the 16 bit or 24 bit address (depending on whether the
     assembler is in segmented or unsegmented mode) of the operand is
     in the instruction.

`address(rN)'
     Indexed: the 16 or 24 bit address is added to the 16 bit register
     to produce the final address in memory of the operand.

`rN(#IMM)'
     Base Address: the 16 or 24 bit register is added to the 16 bit sign
     extended immediate displacement to produce the final address in
     memory of the operand.

`rN(rM)'
     Base Index: the 16 or 24 bit register rN is added to the sign
     extended 16 bit index register rM to produce the final address in
     memory of the operand.

`#XX'
     Immediate data XX.


File: m68k-rtems-as.info,  Node: Z8000 Directives,  Next: Z8000 Opcodes,  Prev: Z8000 Syntax,  Up: Z8000-Dependent

Assembler Directives for the Z8000
----------------------------------

The Z8000 port of as includes these additional assembler directives,
for compatibility with other Z8000 assemblers.  As shown, these do not
begin with `.' (unlike the ordinary as directives).

`segm'
     Generates code for the segmented Z8001.

`unsegm'
     Generates code for the unsegmented Z8002.

`name'
     Synonym for `.file'

`global'
     Synonym for `.global'

`wval'
     Synonym for `.word'

`lval'
     Synonym for `.long'

`bval'
     Synonym for `.byte'

`sval'
     Assemble a string.  `sval' expects one string literal, delimited by
     single quotes.  It assembles each byte of the string into
     consecutive addresses.  You can use the escape sequence `%XX'
     (where XX represents a two-digit hexadecimal number) to represent
     the character whose ASCII value is XX.  Use this feature to
     describe single quote and other characters that may not appear in
     string literals as themselves.  For example, the C statement
     `char *a = "he said \"it's 50% off\"";' is represented in Z8000
     assembly language (shown with the assembler output in hex at the
     left) as

          68652073    sval    'he said %22it%27s 50%25 off%22%00'
          61696420
          22697427
          73203530
          25206F66
          662200

`rsect'
     synonym for `.section'

`block'
     synonym for `.space'

`even'
     special case of `.align'; aligns output to even byte boundary.


File: m68k-rtems-as.info,  Node: Z8000 Opcodes,  Prev: Z8000 Directives,  Up: Z8000-Dependent

Opcodes
-------

For detailed information on the Z8000 machine instruction set, see
`Z8000 Technical Manual'.

   The following table summarizes the opcodes and their arguments:

                 rs   16 bit source register
                 rd   16 bit destination register
                 rbs   8 bit source register
                 rbd   8 bit destination register
                 rrs   32 bit source register
                 rrd   32 bit destination register
                 rqs   64 bit source register
                 rqd   64 bit destination register
                 addr 16/24 bit address
                 imm  immediate data
     
     adc rd,rs               clrb addr               cpsir @rd,@rs,rr,cc
     adcb rbd,rbs            clrb addr(rd)           cpsirb @rd,@rs,rr,cc
     add rd,@rs              clrb rbd                dab rbd
     add rd,addr             com @rd                 dbjnz rbd,disp7
     add rd,addr(rs)         com addr                dec @rd,imm4m1
     add rd,imm16            com addr(rd)            dec addr(rd),imm4m1
     add rd,rs               com rd                  dec addr,imm4m1
     addb rbd,@rs            comb @rd                dec rd,imm4m1
     addb rbd,addr           comb addr               decb @rd,imm4m1
     addb rbd,addr(rs)       comb addr(rd)           decb addr(rd),imm4m1
     addb rbd,imm8           comb rbd                decb addr,imm4m1
     addb rbd,rbs            comflg flags            decb rbd,imm4m1
     addl rrd,@rs            cp @rd,imm16            di i2
     addl rrd,addr           cp addr(rd),imm16       div rrd,@rs
     addl rrd,addr(rs)       cp addr,imm16           div rrd,addr
     addl rrd,imm32          cp rd,@rs               div rrd,addr(rs)
     addl rrd,rrs            cp rd,addr              div rrd,imm16
     and rd,@rs              cp rd,addr(rs)          div rrd,rs
     and rd,addr             cp rd,imm16             divl rqd,@rs
     and rd,addr(rs)         cp rd,rs                divl rqd,addr
     and rd,imm16            cpb @rd,imm8            divl rqd,addr(rs)
     and rd,rs               cpb addr(rd),imm8       divl rqd,imm32
     andb rbd,@rs            cpb addr,imm8           divl rqd,rrs
     andb rbd,addr           cpb rbd,@rs             djnz rd,disp7
     andb rbd,addr(rs)       cpb rbd,addr            ei i2
     andb rbd,imm8           cpb rbd,addr(rs)        ex rd,@rs
     andb rbd,rbs            cpb rbd,imm8            ex rd,addr
     bit @rd,imm4            cpb rbd,rbs             ex rd,addr(rs)
     bit addr(rd),imm4       cpd rd,@rs,rr,cc        ex rd,rs
     bit addr,imm4           cpdb rbd,@rs,rr,cc      exb rbd,@rs
     bit rd,imm4             cpdr rd,@rs,rr,cc       exb rbd,addr
     bit rd,rs               cpdrb rbd,@rs,rr,cc     exb rbd,addr(rs)
     bitb @rd,imm4           cpi rd,@rs,rr,cc        exb rbd,rbs
     bitb addr(rd),imm4      cpib rbd,@rs,rr,cc      ext0e imm8
     bitb addr,imm4          cpir rd,@rs,rr,cc       ext0f imm8
     bitb rbd,imm4           cpirb rbd,@rs,rr,cc     ext8e imm8
     bitb rbd,rs             cpl rrd,@rs             ext8f imm8
     bpt                     cpl rrd,addr            exts rrd
     call @rd                cpl rrd,addr(rs)        extsb rd
     call addr               cpl rrd,imm32           extsl rqd
     call addr(rd)           cpl rrd,rrs             halt
     calr disp12             cpsd @rd,@rs,rr,cc      in rd,@rs
     clr @rd                 cpsdb @rd,@rs,rr,cc     in rd,imm16
     clr addr                cpsdr @rd,@rs,rr,cc     inb rbd,@rs
     clr addr(rd)            cpsdrb @rd,@rs,rr,cc    inb rbd,imm16
     clr rd                  cpsi @rd,@rs,rr,cc      inc @rd,imm4m1
     clrb @rd                cpsib @rd,@rs,rr,cc     inc addr(rd),imm4m1
     inc addr,imm4m1         ldb rbd,rs(rx)          mult rrd,addr(rs)
     inc rd,imm4m1           ldb rd(imm16),rbs       mult rrd,imm16
     incb @rd,imm4m1         ldb rd(rx),rbs          mult rrd,rs
     incb addr(rd),imm4m1    ldctl ctrl,rs           multl rqd,@rs
     incb addr,imm4m1        ldctl rd,ctrl           multl rqd,addr
     incb rbd,imm4m1         ldd @rs,@rd,rr          multl rqd,addr(rs)
     ind @rd,@rs,ra          lddb @rs,@rd,rr         multl rqd,imm32
     indb @rd,@rs,rba        lddr @rs,@rd,rr         multl rqd,rrs
     inib @rd,@rs,ra         lddrb @rs,@rd,rr        neg @rd
     inibr @rd,@rs,ra        ldi @rd,@rs,rr          neg addr
     iret                    ldib @rd,@rs,rr         neg addr(rd)
     jp cc,@rd               ldir @rd,@rs,rr         neg rd
     jp cc,addr              ldirb @rd,@rs,rr        negb @rd
     jp cc,addr(rd)          ldk rd,imm4             negb addr
     jr cc,disp8             ldl @rd,rrs             negb addr(rd)
     ld @rd,imm16            ldl addr(rd),rrs        negb rbd
     ld @rd,rs               ldl addr,rrs            nop
     ld addr(rd),imm16       ldl rd(imm16),rrs       or rd,@rs
     ld addr(rd),rs          ldl rd(rx),rrs          or rd,addr
     ld addr,imm16           ldl rrd,@rs             or rd,addr(rs)
     ld addr,rs              ldl rrd,addr            or rd,imm16
     ld rd(imm16),rs         ldl rrd,addr(rs)        or rd,rs
     ld rd(rx),rs            ldl rrd,imm32           orb rbd,@rs
     ld rd,@rs               ldl rrd,rrs             orb rbd,addr
     ld rd,addr              ldl rrd,rs(imm16)       orb rbd,addr(rs)
     ld rd,addr(rs)          ldl rrd,rs(rx)          orb rbd,imm8
     ld rd,imm16             ldm @rd,rs,n            orb rbd,rbs
     ld rd,rs                ldm addr(rd),rs,n       out @rd,rs
     ld rd,rs(imm16)         ldm addr,rs,n           out imm16,rs
     ld rd,rs(rx)            ldm rd,@rs,n            outb @rd,rbs
     lda rd,addr             ldm rd,addr(rs),n       outb imm16,rbs
     lda rd,addr(rs)         ldm rd,addr,n           outd @rd,@rs,ra
     lda rd,rs(imm16)        ldps @rs                outdb @rd,@rs,rba
     lda rd,rs(rx)           ldps addr               outib @rd,@rs,ra
     ldar rd,disp16          ldps addr(rs)           outibr @rd,@rs,ra
     ldb @rd,imm8            ldr disp16,rs           pop @rd,@rs
     ldb @rd,rbs             ldr rd,disp16           pop addr(rd),@rs
     ldb addr(rd),imm8       ldrb disp16,rbs         pop addr,@rs
     ldb addr(rd),rbs        ldrb rbd,disp16         pop rd,@rs
     ldb addr,imm8           ldrl disp16,rrs         popl @rd,@rs
     ldb addr,rbs            ldrl rrd,disp16         popl addr(rd),@rs
     ldb rbd,@rs             mbit                    popl addr,@rs
     ldb rbd,addr            mreq rd                 popl rrd,@rs
     ldb rbd,addr(rs)        mres                    push @rd,@rs
     ldb rbd,imm8            mset                    push @rd,addr
     ldb rbd,rbs             mult rrd,@rs            push @rd,addr(rs)
     ldb rbd,rs(imm16)       mult rrd,addr           push @rd,imm16
     push @rd,rs             set addr,imm4           subl rrd,imm32
     pushl @rd,@rs           set rd,imm4             subl rrd,rrs
     pushl @rd,addr          set rd,rs               tcc cc,rd
     pushl @rd,addr(rs)      setb @rd,imm4           tccb cc,rbd
     pushl @rd,rrs           setb addr(rd),imm4      test @rd
     res @rd,imm4            setb addr,imm4          test addr
     res addr(rd),imm4       setb rbd,imm4           test addr(rd)
     res addr,imm4           setb rbd,rs             test rd
     res rd,imm4             setflg imm4             testb @rd
     res rd,rs               sinb rbd,imm16          testb addr
     resb @rd,imm4           sinb rd,imm16           testb addr(rd)
     resb addr(rd),imm4      sind @rd,@rs,ra         testb rbd
     resb addr,imm4          sindb @rd,@rs,rba       testl @rd
     resb rbd,imm4           sinib @rd,@rs,ra        testl addr
     resb rbd,rs             sinibr @rd,@rs,ra       testl addr(rd)
     resflg imm4             sla rd,imm8             testl rrd
     ret cc                  slab rbd,imm8           trdb @rd,@rs,rba
     rl rd,imm1or2           slal rrd,imm8           trdrb @rd,@rs,rba
     rlb rbd,imm1or2         sll rd,imm8             trib @rd,@rs,rbr
     rlc rd,imm1or2          sllb rbd,imm8           trirb @rd,@rs,rbr
     rlcb rbd,imm1or2        slll rrd,imm8           trtdrb @ra,@rb,rbr
     rldb rbb,rba            sout imm16,rs           trtib @ra,@rb,rr
     rr rd,imm1or2           soutb imm16,rbs         trtirb @ra,@rb,rbr
     rrb rbd,imm1or2         soutd @rd,@rs,ra        trtrb @ra,@rb,rbr
     rrc rd,imm1or2          soutdb @rd,@rs,rba      tset @rd
     rrcb rbd,imm1or2        soutib @rd,@rs,ra       tset addr
     rrdb rbb,rba            soutibr @rd,@rs,ra      tset addr(rd)
     rsvd36                  sra rd,imm8             tset rd
     rsvd38                  srab rbd,imm8           tsetb @rd
     rsvd78                  sral rrd,imm8           tsetb addr
     rsvd7e                  srl rd,imm8             tsetb addr(rd)
     rsvd9d                  srlb rbd,imm8           tsetb rbd
     rsvd9f                  srll rrd,imm8           xor rd,@rs
     rsvdb9                  sub rd,@rs              xor rd,addr
     rsvdbf                  sub rd,addr             xor rd,addr(rs)
     sbc rd,rs               sub rd,addr(rs)         xor rd,imm16
     sbcb rbd,rbs            sub rd,imm16            xor rd,rs
     sc imm8                 sub rd,rs               xorb rbd,@rs
     sda rd,rs               subb rbd,@rs            xorb rbd,addr
     sdab rbd,rs             subb rbd,addr           xorb rbd,addr(rs)
     sdal rrd,rs             subb rbd,addr(rs)       xorb rbd,imm8
     sdl rd,rs               subb rbd,imm8           xorb rbd,rbs
     sdlb rbd,rs             subb rbd,rbs            xorb rbd,rbs
     sdll rrd,rs             subl rrd,@rs
     set @rd,imm4            subl rrd,addr
     set addr(rd),imm4       subl rrd,addr(rs)


File: m68k-rtems-as.info,  Node: Vax-Dependent,  Prev: Z8000-Dependent,  Up: Machine Dependencies

VAX Dependent Features
======================

* Menu:

* VAX-Opts::                    VAX Command-Line Options
* VAX-float::                   VAX Floating Point
* VAX-directives::              Vax Machine Directives
* VAX-opcodes::                 VAX Opcodes
* VAX-branch::                  VAX Branch Improvement
* VAX-operands::                VAX Operands
* VAX-no::                      Not Supported on VAX


File: m68k-rtems-as.info,  Node: VAX-Opts,  Next: VAX-float,  Up: Vax-Dependent

VAX Command-Line Options
------------------------

The Vax version of `as' accepts any of the following options, gives a
warning message that the option was ignored and proceeds.  These
options are for compatibility with scripts designed for other people's
assemblers.

``-D' (Debug)'
``-S' (Symbol Table)'
``-T' (Token Trace)'
     These are obsolete options used to debug old assemblers.

``-d' (Displacement size for JUMPs)'
     This option expects a number following the `-d'.  Like options
     that expect filenames, the number may immediately follow the `-d'
     (old standard) or constitute the whole of the command line
     argument that follows `-d' (GNU standard).

``-V' (Virtualize Interpass Temporary File)'
     Some other assemblers use a temporary file.  This option commanded
     them to keep the information in active memory rather than in a
     disk file.  `as' always does this, so this option is redundant.

``-J' (JUMPify Longer Branches)'
     Many 32-bit computers permit a variety of branch instructions to
     do the same job.  Some of these instructions are short (and fast)
     but have a limited range; others are long (and slow) but can
     branch anywhere in virtual memory.  Often there are 3 flavors of
     branch: short, medium and long.  Some other assemblers would emit
     short and medium branches, unless told by this option to emit
     short and long branches.

``-t' (Temporary File Directory)'
     Some other assemblers may use a temporary file, and this option
     takes a filename being the directory to site the temporary file.
     Since `as' does not use a temporary disk file, this option makes
     no difference.  `-t' needs exactly one filename.

   The Vax version of the assembler accepts additional options when
compiled for VMS:

`-h N'
     External symbol or section (used for global variables) names are
     not case sensitive on VAX/VMS and always mapped to upper case.
     This is contrary to the C language definition which explicitly
     distinguishes upper and lower case.  To implement a standard
     conforming C compiler, names must be changed (mapped) to preserve
     the case information.  The default mapping is to convert all lower
     case characters to uppercase and adding an underscore followed by
     a 6 digit hex value, representing a 24 digit binary value.  The
     one digits in the binary value represent which characters are
     uppercase in the original symbol name.

     The `-h N' option determines how we map names.  This takes several
     values.  No `-h' switch at all allows case hacking as described
     above.  A value of zero (`-h0') implies names should be upper
     case, and inhibits the case hack.  A value of 2 (`-h2') implies
     names should be all lower case, with no case hack.  A value of 3
     (`-h3') implies that case should be preserved.  The value 1 is
     unused.  The `-H' option directs `as' to display every mapped
     symbol during assembly.

     Symbols whose names include a dollar sign `$' are exceptions to the
     general name mapping.  These symbols are normally only used to
     reference VMS library names.  Such symbols are always mapped to
     upper case.

`-+'
     The `-+' option causes `as' to truncate any symbol name larger
     than 31 characters.  The `-+' option also prevents some code
     following the `_main' symbol normally added to make the object
     file compatible with Vax-11 "C".

`-1'
     This option is ignored for backward compatibility with `as'
     version 1.x.

`-H'
     The `-H' option causes `as' to print every symbol which was
     changed by case mapping.


File: m68k-rtems-as.info,  Node: VAX-float,  Next: VAX-directives,  Prev: VAX-Opts,  Up: Vax-Dependent

VAX Floating Point
------------------

Conversion of flonums to floating point is correct, and compatible with
previous assemblers.  Rounding is towards zero if the remainder is
exactly half the least significant bit.

   `D', `F', `G' and `H' floating point formats are understood.

   Immediate floating literals (_e.g._ `S`$6.9') are rendered
correctly.  Again, rounding is towards zero in the boundary case.

   The `.float' directive produces `f' format numbers.  The `.double'
directive produces `d' format numbers.


File: m68k-rtems-as.info,  Node: VAX-directives,  Next: VAX-opcodes,  Prev: VAX-float,  Up: Vax-Dependent

Vax Machine Directives
----------------------

The Vax version of the assembler supports four directives for
generating Vax floating point constants.  They are described in the
table below.

`.dfloat'
     This expects zero or more flonums, separated by commas, and
     assembles Vax `d' format 64-bit floating point constants.

`.ffloat'
     This expects zero or more flonums, separated by commas, and
     assembles Vax `f' format 32-bit floating point constants.

`.gfloat'
     This expects zero or more flonums, separated by commas, and
     assembles Vax `g' format 64-bit floating point constants.

`.hfloat'
     This expects zero or more flonums, separated by commas, and
     assembles Vax `h' format 128-bit floating point constants.



File: m68k-rtems-as.info,  Node: VAX-opcodes,  Next: VAX-branch,  Prev: VAX-directives,  Up: Vax-Dependent

VAX Opcodes
-----------

All DEC mnemonics are supported.  Beware that `case...' instructions
have exactly 3 operands.  The dispatch table that follows the `case...'
instruction should be made with `.word' statements.  This is compatible
with all unix assemblers we know of.


File: m68k-rtems-as.info,  Node: VAX-branch,  Next: VAX-operands,  Prev: VAX-opcodes,  Up: Vax-Dependent

VAX Branch Improvement
----------------------

Certain pseudo opcodes are permitted.  They are for branch
instructions.  They expand to the shortest branch instruction that
reaches the target.  Generally these mnemonics are made by substituting
`j' for `b' at the start of a DEC mnemonic.  This feature is included
both for compatibility and to help compilers.  If you do not need this
feature, avoid these opcodes.  Here are the mnemonics, and the code
they can expand into.

`jbsb'
     `Jsb' is already an instruction mnemonic, so we chose `jbsb'.
    (byte displacement)
          `bsbb ...'

    (word displacement)
          `bsbw ...'

    (long displacement)
          `jsb ...'

`jbr'
`jr'
     Unconditional branch.
    (byte displacement)
          `brb ...'

    (word displacement)
          `brw ...'

    (long displacement)
          `jmp ...'

`jCOND'
     COND may be any one of the conditional branches `neq', `nequ',
     `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs',
     `gequ', `cc', `lssu', `cs'.  COND may also be one of the bit tests
     `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs',
     `lbc'.  NOTCOND is the opposite condition to COND.
    (byte displacement)
          `bCOND ...'

    (word displacement)
          `bNOTCOND foo ; brw ... ; foo:'

    (long displacement)
          `bNOTCOND foo ; jmp ... ; foo:'

`jacbX'
     X may be one of `b d f g h l w'.
    (word displacement)
          `OPCODE ...'

    (long displacement)
               OPCODE ..., foo ;
               brb bar ;
               foo: jmp ... ;
               bar:

`jaobYYY'
     YYY may be one of `lss leq'.

`jsobZZZ'
     ZZZ may be one of `geq gtr'.
    (byte displacement)
          `OPCODE ...'

    (word displacement)
               OPCODE ..., foo ;
               brb bar ;
               foo: brw DESTINATION ;
               bar:

    (long displacement)
               OPCODE ..., foo ;
               brb bar ;
               foo: jmp DESTINATION ;
               bar:

`aobleq'
`aoblss'
`sobgeq'
`sobgtr'

    (byte displacement)
          `OPCODE ...'

    (word displacement)
               OPCODE ..., foo ;
               brb bar ;
               foo: brw DESTINATION ;
               bar:

    (long displacement)
               OPCODE ..., foo ;
               brb bar ;
               foo: jmp DESTINATION ;
               bar:


File: m68k-rtems-as.info,  Node: VAX-operands,  Next: VAX-no,  Prev: VAX-branch,  Up: Vax-Dependent

VAX Operands
------------

The immediate character is `$' for Unix compatibility, not `#' as DEC
writes it.

   The indirect character is `*' for Unix compatibility, not `@' as DEC
writes it.

   The displacement sizing character is ``' (an accent grave) for Unix
compatibility, not `^' as DEC writes it.  The letter preceding ``' may
have either case.  `G' is not understood, but all other letters (`b i l
s w') are understood.

   Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'.  Upper
and lower case letters are equivalent.

   For instance
     tstb *w`$4(r5)

   Any expression is permitted in an operand.  Operands are comma
separated.


File: m68k-rtems-as.info,  Node: VAX-no,  Prev: VAX-operands,  Up: Vax-Dependent

Not Supported on VAX
--------------------

Vax bit fields can not be assembled with `as'.  Someone can add the
required code if they really need it.


File: m68k-rtems-as.info,  Node: V850-Dependent,  Next: Z8000-Dependent,  Prev: Sparc-Dependent,  Up: Machine Dependencies

v850 Dependent Features
=======================

* Menu:

* V850 Options::              Options
* V850 Syntax::               Syntax
* V850 Floating Point::       Floating Point
* V850 Directives::           V850 Machine Directives
* V850 Opcodes::              Opcodes


File: m68k-rtems-as.info,  Node: V850 Options,  Next: V850 Syntax,  Up: V850-Dependent

Options
-------

`as' supports the following additional command-line options for the
V850 processor family:

`-wsigned_overflow'
     Causes warnings to be produced when signed immediate values
     overflow the space available for then within their opcodes.  By
     default this option is disabled as it is possible to receive
     spurious warnings due to using exact bit patterns as immediate
     constants.

`-wunsigned_overflow'
     Causes warnings to be produced when unsigned immediate values
     overflow the space available for then within their opcodes.  By
     default this option is disabled as it is possible to receive
     spurious warnings due to using exact bit patterns as immediate
     constants.

`-mv850'
     Specifies that the assembled code should be marked as being
     targeted at the V850 processor.  This allows the linker to detect
     attempts to link such code with code assembled for other
     processors.

`-mv850e'
     Specifies that the assembled code should be marked as being
     targeted at the V850E processor.  This allows the linker to detect
     attempts to link such code with code assembled for other
     processors.

`-mv850any'
     Specifies that the assembled code should be marked as being
     targeted at the V850 processor but support instructions that are
     specific to the extended variants of the process.  This allows the
     production of binaries that contain target specific code, but
     which are also intended to be used in a generic fashion.  For
     example libgcc.a contains generic routines used by the code
     produced by GCC for all versions of the v850 architecture,
     together with support routines only used by the V850E architecture.



File: m68k-rtems-as.info,  Node: V850 Syntax,  Next: V850 Floating Point,  Prev: V850 Options,  Up: V850-Dependent

Syntax
------

* Menu:

* V850-Chars::                Special Characters
* V850-Regs::                 Register Names


File: m68k-rtems-as.info,  Node: V850-Chars,  Next: V850-Regs,  Up: V850 Syntax

Special Characters
..................

`#' is the line comment character.


File: m68k-rtems-as.info,  Node: V850-Regs,  Prev: V850-Chars,  Up: V850 Syntax

Register Names
..............

`as' supports the following names for registers:
`general register 0'
     r0, zero

`general register 1'
     r1

`general register 2'
     r2, hp

`general register 3'
     r3, sp

`general register 4'
     r4, gp

`general register 5'
     r5, tp

`general register 6'
     r6

`general register 7'
     r7

`general register 8'
     r8

`general register 9'
     r9

`general register 10'
     r10

`general register 11'
     r11

`general register 12'
     r12

`general register 13'
     r13

`general register 14'
     r14

`general register 15'
     r15

`general register 16'
     r16

`general register 17'
     r17

`general register 18'
     r18

`general register 19'
     r19

`general register 20'
     r20

`general register 21'
     r21

`general register 22'
     r22

`general register 23'
     r23

`general register 24'
     r24

`general register 25'
     r25

`general register 26'
     r26

`general register 27'
     r27

`general register 28'
     r28

`general register 29'
     r29

`general register 30'
     r30, ep

`general register 31'
     r31, lp

`system register 0'
     eipc

`system register 1'
     eipsw

`system register 2'
     fepc

`system register 3'
     fepsw

`system register 4'
     ecr

`system register 5'
     psw

`system register 16'
     ctpc

`system register 17'
     ctpsw

`system register 18'
     dbpc

`system register 19'
     dbpsw

`system register 20'
     ctbp


File: m68k-rtems-as.info,  Node: V850 Floating Point,  Next: V850 Directives,  Prev: V850 Syntax,  Up: V850-Dependent

Floating Point
--------------

The V850 family uses IEEE floating-point numbers.


File: m68k-rtems-as.info,  Node: V850 Directives,  Next: V850 Opcodes,  Prev: V850 Floating Point,  Up: V850-Dependent

V850 Machine Directives
-----------------------

`.offset <EXPRESSION>'
     Moves the offset into the current section to the specified amount.

`.section "name", <type>'
     This is an extension to the standard .section directive.  It sets
     the current section to be <type> and creates an alias for this
     section called "name".

`.v850'
     Specifies that the assembled code should be marked as being
     targeted at the V850 processor.  This allows the linker to detect
     attempts to link such code with code assembled for other
     processors.

`.v850e'
     Specifies that the assembled code should be marked as being
     targeted at the V850E processor.  This allows the linker to detect
     attempts to link such code with code assembled for other
     processors.



File: m68k-rtems-as.info,  Node: V850 Opcodes,  Prev: V850 Directives,  Up: V850-Dependent

Opcodes
-------

`as' implements all the standard V850 opcodes.

   `as' also implements the following pseudo ops:

`hi0()'
     Computes the higher 16 bits of the given expression and stores it
     into the immediate operand field of the given instruction.  For
     example:

     `mulhi hi0(here - there), r5, r6'

     computes the difference between the address of labels 'here' and
     'there', takes the upper 16 bits of this difference, shifts it
     down 16 bits and then mutliplies it by the lower 16 bits in
     register 5, putting the result into register 6.

`lo()'
     Computes the lower 16 bits of the given expression and stores it
     into the immediate operand field of the given instruction.  For
     example:

     `addi lo(here - there), r5, r6'

     computes the difference between the address of labels 'here' and
     'there', takes the lower 16 bits of this difference and adds it to
     register 5, putting the result into register 6.

`hi()'
     Computes the higher 16 bits of the given expression and then adds
     the value of the most significant bit of the lower 16 bits of the
     expression and stores the result into the immediate operand field
     of the given instruction.  For example the following code can be
     used to compute the address of the label 'here' and store it into
     register 6:

     `movhi hi(here), r0, r6'     `movea lo(here), r6, r6'

     The reason for this special behaviour is that movea performs a sign
     extention on its immediate operand.  So for example if the address
     of 'here' was 0xFFFFFFFF then without the special behaviour of the
     hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6,
     then the movea instruction would takes its immediate operand,
     0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it
     into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E).
     With the hi() pseudo op adding in the top bit of the lo() pseudo
     op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 =
     0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 -
     the right value.

`hilo()'
     Computes the 32 bit value of the given expression and stores it
     into the immediate operand field of the given instruction (which
     must be a mov instruction).  For example:

     `mov hilo(here), r6'

     computes the absolute address of label 'here' and puts the result
     into register 6.

`sdaoff()'
     Computes the offset of the named variable from the start of the
     Small Data Area (whoes address is held in register 4, the GP
     register) and stores the result as a 16 bit signed value in the
     immediate operand field of the given instruction.  For example:

     `ld.w sdaoff(_a_variable)[gp],r6'

     loads the contents of the location pointed to by the label
     '_a_variable' into register 6, provided that the label is located
     somewhere within +/- 32K of the address held in the GP register.
     [Note the linker assumes that the GP register contains a fixed
     address set to the address of the label called '__gp'.  This can
     either be set up automatically by the linker, or specifically set
     by using the `--defsym __gp=<value>' command line option].

`tdaoff()'
     Computes the offset of the named variable from the start of the
     Tiny Data Area (whoes address is held in register 30, the EP
     register) and stores the result as a 4,5, 7 or 8 bit unsigned
     value in the immediate operand field of the given instruction.
     For example:

     `sld.w tdaoff(_a_variable)[ep],r6'

     loads the contents of the location pointed to by the label
     '_a_variable' into register 6, provided that the label is located
     somewhere within +256 bytes of the address held in the EP
     register.  [Note the linker assumes that the EP register contains
     a fixed address set to the address of the label called '__ep'.
     This can either be set up automatically by the linker, or
     specifically set by using the `--defsym __ep=<value>' command line
     option].

`zdaoff()'
     Computes the offset of the named variable from address 0 and
     stores the result as a 16 bit signed value in the immediate
     operand field of the given instruction.  For example:

     `movea zdaoff(_a_variable),zero,r6'

     puts the address of the label '_a_variable' into register 6,
     assuming that the label is somewhere within the first 32K of
     memory.  (Strictly speaking it also possible to access the last
     32K of memory as well, as the offsets are signed).

`ctoff()'
     Computes the offset of the named variable from the start of the
     Call Table Area (whoes address is helg in system register 20, the
     CTBP register) and stores the result a 6 or 16 bit unsigned value
     in the immediate field of then given instruction or piece of data.
     For example:

     `callt ctoff(table_func1)'

     will put the call the function whoes address is held in the call
     table at the location labeled 'table_func1'.


   For information on the V850 instruction set, see `V850 Family
32-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC.
Ltd.


File: m68k-rtems-as.info,  Node: Reporting Bugs,  Next: Acknowledgements,  Prev: Machine Dependencies,  Up: Top

Reporting Bugs
**************

Your bug reports play an essential role in making `as' reliable.

   Reporting a bug may help you by bringing a solution to your problem,
or it may not.  But in any case the principal function of a bug report
is to help the entire community by making the next version of `as' work
better.  Bug reports are your contribution to the maintenance of `as'.

   In order for a bug report to serve its purpose, you must include the
information that enables us to fix the bug.

* Menu:

* Bug Criteria::                Have you found a bug?
* Bug Reporting::               How to report bugs


File: m68k-rtems-as.info,  Node: Bug Criteria,  Next: Bug Reporting,  Up: Reporting Bugs

Have you found a bug?
=====================

If you are not sure whether you have found a bug, here are some
guidelines:

   * If the assembler gets a fatal signal, for any input whatever, that
     is a `as' bug.  Reliable assemblers never crash.

   * If `as' produces an error message for valid input, that is a bug.

   * If `as' does not produce an error message for invalid input, that
     is a bug.  However, you should note that your idea of "invalid
     input" might be our idea of "an extension" or "support for
     traditional practice".

   * If you are an experienced user of assemblers, your suggestions for
     improvement of `as' are welcome in any case.


File: m68k-rtems-as.info,  Node: Bug Reporting,  Prev: Bug Criteria,  Up: Reporting Bugs

How to report bugs
==================

A number of companies and individuals offer support for GNU products.
If you obtained `as' from a support organization, we recommend you
contact that organization first.

   You can find contact information for many support companies and
individuals in the file `etc/SERVICE' in the GNU Emacs distribution.

   In any event, we also recommend that you send bug reports for `as'
to `bug-binutils@gnu.org'.

   The fundamental principle of reporting bugs usefully is this:
*report all the facts*.  If you are not sure whether to state a fact or
leave it out, state it!

   Often people omit facts because they think they know what causes the
problem and assume that some details do not matter.  Thus, you might
assume that the name of a symbol you use in an example does not matter.
Well, probably it does not, but one cannot be sure.  Perhaps the bug
is a stray memory reference which happens to fetch from the location
where that name is stored in memory; perhaps, if the name were
different, the contents of that location would fool the assembler into
doing the right thing despite the bug.  Play it safe and give a
specific, complete example.  That is the easiest thing for you to do,
and the most helpful.

   Keep in mind that the purpose of a bug report is to enable us to fix
the bug if it is new to us.  Therefore, always write your bug reports
on the assumption that the bug has not been reported previously.

   Sometimes people give a few sketchy facts and ask, "Does this ring a
bell?"  Those bug reports are useless, and we urge everyone to _refuse
to respond to them_ except to chide the sender to report bugs properly.

   To enable us to fix the bug, you should include all these things:

   * The version of `as'.  `as' announces it if you start it with the
     `--version' argument.

     Without this, we will not know whether there is any point in
     looking for the bug in the current version of `as'.

   * Any patches you may have applied to the `as' source.

   * The type of machine you are using, and the operating system name
     and version number.

   * What compiler (and its version) was used to compile `as'--e.g.
     "`gcc-2.7'".

   * The command arguments you gave the assembler to assemble your
     example and observe the bug.  To guarantee you will not omit
     something important, list them all.  A copy of the Makefile (or
     the output from make) is sufficient.

     If we were to try to guess the arguments, we would probably guess
     wrong and then we might not encounter the bug.

   * A complete input file that will reproduce the bug.  If the bug is
     observed when the assembler is invoked via a compiler, send the
     assembler source, not the high level language source.  Most
     compilers will produce the assembler source when run with the `-S'
     option.  If you are using `gcc', use the options `-v
     --save-temps'; this will save the assembler source in a file with
     an extension of `.s', and also show you exactly how `as' is being
     run.

   * A description of what behavior you observe that you believe is
     incorrect.  For example, "It gets a fatal signal."

     Of course, if the bug is that `as' gets a fatal signal, then we
     will certainly notice it.  But if the bug is incorrect output, we
     might not notice unless it is glaringly wrong.  You might as well
     not give us a chance to make a mistake.

     Even if the problem you experience is a fatal signal, you should
     still say so explicitly.  Suppose something strange is going on,
     such as, your copy of `as' is out of synch, or you have
     encountered a bug in the C library on your system.  (This has
     happened!)  Your copy might crash and ours would not.  If you told
     us to expect a crash, then when ours fails to crash, we would know
     that the bug was not happening for us.  If you had not told us to
     expect a crash, then we would not be able to draw any conclusion
     from our observations.

   * If you wish to suggest changes to the `as' source, send us context
     diffs, as generated by `diff' with the `-u', `-c', or `-p' option.
     Always send diffs from the old file to the new file.  If you even
     discuss something in the `as' source, refer to it by context, not
     by line number.

     The line numbers in our development sources will not match those
     in your sources.  Your line numbers would convey no useful
     information to us.

   Here are some things that are not necessary:

   * A description of the envelope of the bug.

     Often people who encounter a bug spend a lot of time investigating
     which changes to the input file will make the bug go away and which
     changes will not affect it.

     This is often time consuming and not very useful, because the way
     we will find the bug is by running a single example under the
     debugger with breakpoints, not by pure deduction from a series of
     examples.  We recommend that you save your time for something else.

     Of course, if you can find a simpler example to report _instead_
     of the original one, that is a convenience for us.  Errors in the
     output will be easier to spot, running under the debugger will take
     less time, and so on.

     However, simplification is not vital; if you do not want to do
     this, report the bug anyway and send us the entire test case you
     used.

   * A patch for the bug.

     A patch for the bug does help us if it is a good one.  But do not
     omit the necessary information, such as the test case, on the
     assumption that a patch is all we need.  We might see problems
     with your patch and decide to fix the problem another way, or we
     might not understand it at all.

     Sometimes with a program as complicated as `as' it is very hard to
     construct an example that will make the program follow a certain
     path through the code.  If you do not send us the example, we will
     not be able to construct one, so we will not be able to verify
     that the bug is fixed.

     And if we cannot understand what bug you are trying to fix, or why
     your patch should be an improvement, we will not install it.  A
     test case will help us to understand.

   * A guess about what the bug is or what it depends on.

     Such guesses are usually wrong.  Even we cannot guess right about
     such things without first using the debugger to find the facts.


File: m68k-rtems-as.info,  Node: Acknowledgements,  Next: GNU Free Documentation License,  Prev: Reporting Bugs,  Up: Top

Acknowledgements
****************

If you have contributed to `as' and your name isn't listed here, it is
not meant as a slight.  We just don't know about it.  Send mail to the
maintainer, and we'll correct the situation.  Currently the maintainer
is Ken Raeburn (email address `raeburn@cygnus.com').

   Dean Elsner wrote the original GNU assembler for the VAX.(1)

   Jay Fenlason maintained GAS for a while, adding support for
GDB-specific debug information and the 68k series machines, most of the
preprocessing pass, and extensive changes in `messages.c',
`input-file.c', `write.c'.

   K. Richard Pixley maintained GAS for a while, adding various
enhancements and many bug fixes, including merging support for several
processors, breaking GAS up to handle multiple object file format back
ends (including heavy rewrite, testing, an integration of the coff and
b.out back ends), adding configuration including heavy testing and
verification of cross assemblers and file splits and renaming,
converted GAS to strictly ANSI C including full prototypes, added
support for m680[34]0 and cpu32, did considerable work on i960
including a COFF port (including considerable amounts of reverse
engineering), a SPARC opcode file rewrite, DECstation, rs6000, and
hp300hpux host ports, updated "know" assertions and made them work,
much other reorganization, cleanup, and lint.

   Ken Raeburn wrote the high-level BFD interface code to replace most
of the code in format-specific I/O modules.

   The original VMS support was contributed by David L. Kashtan.  Eric
Youngdale has done much work with it since.

   The Intel 80386 machine description was written by Eliot Dresselhaus.

   Minh Tran-Le at IntelliCorp contributed some AIX 386 support.

   The Motorola 88k machine description was contributed by Devon Bowen
of Buffalo University and Torbjorn Granlund of the Swedish Institute of
Computer Science.

   Keith Knowles at the Open Software Foundation wrote the original
MIPS back end (`tc-mips.c', `tc-mips.h'), and contributed Rose format
support (which hasn't been merged in yet).  Ralph Campbell worked with
the MIPS code to support a.out format.

   Support for the Zilog Z8k and Hitachi H8/300 and H8/500 processors
(tc-z8k, tc-h8300, tc-h8500), and IEEE 695 object file format
(obj-ieee), was written by Steve Chamberlain of Cygnus Support.  Steve
also modified the COFF back end to use BFD for some low-level
operations, for use with the H8/300 and AMD 29k targets.

   John Gilmore built the AMD 29000 support, added `.include' support,
and simplified the configuration of which versions accept which
directives.  He updated the 68k machine description so that Motorola's
opcodes always produced fixed-size instructions (e.g. `jsr'), while
synthetic instructions remained shrinkable (`jbsr').  John fixed many
bugs, including true tested cross-compilation support, and one bug in
relaxation that took a week and required the proverbial one-bit fix.

   Ian Lance Taylor of Cygnus Support merged the Motorola and MIT
syntax for the 68k, completed support for some COFF targets (68k, i386
SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets,
wrote the initial RS/6000 and PowerPC assembler, and made a few other
minor patches.

   Steve Chamberlain made `as' able to generate listings.

   Hewlett-Packard contributed support for the HP9000/300.

   Jeff Law wrote GAS and BFD support for the native HPPA object format
(SOM) along with a fairly extensive HPPA testsuite (for both SOM and
ELF object formats).  This work was supported by both the Center for
Software Science at the University of Utah and Cygnus Support.

   Support for ELF format files has been worked on by Mark Eichin of
Cygnus Support (original, incomplete implementation for SPARC), Pete
Hoogenboom and Jeff Law at the University of Utah (HPPA mainly),
Michael Meissner of the Open Software Foundation (i386 mainly), and Ken
Raeburn of Cygnus Support (sparc, and some initial 64-bit support).

   Linas Vepstas added GAS support for the ESA/390 "IBM 370"
architecture.

   Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote
GAS and BFD support for openVMS/Alpha.

   Timothy Wall, Michael Hayes, and Greg Smart contributed to the
various tic* flavors.

   Several engineers at Cygnus Support have also provided many small
bug fixes and configuration enhancements.

   Many others have contributed large or small bugfixes and
enhancements.  If you have contributed significant work and are not
mentioned on this list, and want to be, let us know.  Some of the
history has been lost; we are not intentionally leaving anyone out.

   ---------- Footnotes ----------

   (1) Any more details?


File: m68k-rtems-as.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Acknowledgements,  Up: Top

GNU Free Documentation License
******************************

GNU Free Documentation License

   Version 1.1, March 2000

   Copyright (C) 2000  Free Software Foundation, Inc.    59 Temple
Place, Suite 330, Boston, MA  02111-1307  USA

   Everyone is permitted to copy and distribute verbatim copies  of
this license document, but changing it is not allowed.

   0. PREAMBLE

   The purpose of this License is to make a manual, textbook, or other
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   You may copy and distribute a Modified Version of the Document under
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   A. Use in the Title Page (and on the covers, if any) a title distinct
  from that of the Document, and from those of previous versions
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the Document.  E. Add an appropriate copyright notice for your
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that license notice the full lists of Invariant Sections    and
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K. In any section entitled "Acknowledgements" or "Dedications",
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   If the Modified Version includes new front-matter sections or
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   You may make a collection consisting of the Document and other
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   You may not copy, modify, sublicense, or distribute the Document
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   10. FUTURE REVISIONS OF THIS LICENSE

   The Free Software Foundation may publish new, revised versions of
the GNU Free Documentation License from time to time.  Such new
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   ADDENDUM: How to use this License for your documents

   To use this License in a document you have written, include a copy of
the License in the document and put the following copyright and license
notices just after the title page:

         Copyright (c)  YEAR  YOUR NAME.
         Permission is granted to copy, distribute and/or modify this document
         under the terms of the GNU Free Documentation License, Version 1.1
         or any later version published by the Free Software Foundation;
         with the Invariant Sections being LIST THEIR TITLES, with the
         Front-Cover Texts being LIST, and with the Back-Cover Texts being LIST.
         A copy of the license is included in the section entitled "GNU
         Free Documentation License".

   If you have no Invariant Sections, write "with no Invariant Sections"
instead of saying which ones are invariant.  If you have no Front-Cover
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LIST"; likewise for Back-Cover Texts.

   If your document contains nontrivial examples of program code, we
recommend releasing these examples in parallel under your choice of
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permit their use in free software.


File: m68k-rtems-as.info,  Node: Index,  Prev: GNU Free Documentation License,  Up: Top

Index
*****

* Menu:

* #:                                     Comments.
* #APP:                                  Preprocessing.
* #NO_APP:                               Preprocessing.
* $ in symbol names <1>:                 H8/500-Chars.
* $ in symbol names <2>:                 SH64-Chars.
* $ in symbol names <3>:                 D30V-Chars.
* $ in symbol names <4>:                 SH-Chars.
* $ in symbol names:                     D10V-Chars.
* -+ option, VAX/VMS:                    VAX-Opts.
* --:                                    Command Line.
* --32 option, i386:                     i386-Options.
* --32 option, x86-64:                   i386-Options.
* --64 option, i386:                     i386-Options.
* --64 option, x86-64:                   i386-Options.
* --base-size-default-16:                M68K-Opts.
* --base-size-default-32:                M68K-Opts.
* --bitwise-or option, M680x0:           M68K-Opts.
* --disp-size-default-16:                M68K-Opts.
* --disp-size-default-32:                M68K-Opts.
* --emulation=crisaout command line option, CRIS: CRIS-Opts.
* --emulation=criself command line option, CRIS: CRIS-Opts.
* --enforce-aligned-data:                Sparc-Aligned-Data.
* --fatal-warnings:                      W.
* --fixed-special-register-names command line option, MMIX: MMIX-Opts.
* --force-long-branchs:                  M68HC11-Opts.
* --generate-example:                    M68HC11-Opts.
* --globalize-symbols command line option, MMIX: MMIX-Opts.
* --gnu-syntax command line option, MMIX: MMIX-Opts.
* --linker-allocated-gregs command line option, MMIX: MMIX-Opts.
* --listing-cont-lines:                  listing.
* --listing-lhs-width:                   listing.
* --listing-lhs-width2:                  listing.
* --listing-rhs-width:                   listing.
* --MD:                                  MD.
* --no-expand command line option, MMIX: MMIX-Opts.
* --no-merge-gregs command line option, MMIX: MMIX-Opts.
* --no-predefined-syms command line option, MMIX: MMIX-Opts.
* --no-underscore command line option, CRIS: CRIS-Opts.
* --no-warn:                             W.
* --pcrel:                               M68K-Opts.
* --pic command line option, CRIS:       CRIS-Opts.
* --print-insn-syntax:                   M68HC11-Opts.
* --print-opcodes:                       M68HC11-Opts.
* --register-prefix-optional option, M680x0: M68K-Opts.
* --relax command line option, MMIX:     MMIX-Opts.
* --short-branchs:                       M68HC11-Opts.
* --statistics:                          statistics.
* --strict-direct-mode:                  M68HC11-Opts.
* --traditional-format:                  traditional-format.
* --underscore command line option, CRIS: CRIS-Opts.
* --warn:                                W.
* -1 option, VAX/VMS:                    VAX-Opts.
* -32addr command line option, Alpha:    Alpha Options.
* -a:                                    a.
* -A options, i960:                      Options-i960.
* -ac:                                   a.
* -ad:                                   a.
* -ah:                                   a.
* -al:                                   a.
* -an:                                   a.
* -as:                                   a.
* -Asparclet:                            Sparc-Opts.
* -Asparclite:                           Sparc-Opts.
* -Av6:                                  Sparc-Opts.
* -Av8:                                  Sparc-Opts.
* -Av9:                                  Sparc-Opts.
* -Av9a:                                 Sparc-Opts.
* -b option, i960:                       Options-i960.
* -big:                                  SH Options.
* -construct-floats:                     MIPS Opts.
* -D:                                    D.
* -D, ignored on VAX:                    VAX-Opts.
* -d, VAX option:                        VAX-Opts.
* -dsp:                                  SH Options.
* -EB command line option, ARC:          ARC Options.
* -EB command line option, ARM:          ARM Options.
* -EB option (MIPS):                     MIPS Opts.
* -EL command line option, ARC:          ARC Options.
* -EL command line option, ARM:          ARM Options.
* -EL option (MIPS):                     MIPS Opts.
* -f:                                    f.
* -F command line option, Alpha:         Alpha Options.
* -G command line option, Alpha:         Alpha Options.
* -g command line option, Alpha:         Alpha Options.
* -G option (MIPS):                      MIPS Opts.
* -h option, VAX/VMS:                    VAX-Opts.
* -H option, VAX/VMS:                    VAX-Opts.
* -I PATH:                               I.
* -J, ignored on VAX:                    VAX-Opts.
* -K:                                    K.
* -k command line option, ARM:           ARM Options.
* -L:                                    L.
* -l option, M680x0:                     M68K-Opts.
* -little:                               SH Options.
* -M:                                    M.
* -m11/03:                               PDP-11-Options.
* -m11/04:                               PDP-11-Options.
* -m11/05:                               PDP-11-Options.
* -m11/10:                               PDP-11-Options.
* -m11/15:                               PDP-11-Options.
* -m11/20:                               PDP-11-Options.
* -m11/21:                               PDP-11-Options.
* -m11/23:                               PDP-11-Options.
* -m11/24:                               PDP-11-Options.
* -m11/34:                               PDP-11-Options.
* -m11/34a:                              PDP-11-Options.
* -m11/35:                               PDP-11-Options.
* -m11/40:                               PDP-11-Options.
* -m11/44:                               PDP-11-Options.
* -m11/45:                               PDP-11-Options.
* -m11/50:                               PDP-11-Options.
* -m11/53:                               PDP-11-Options.
* -m11/55:                               PDP-11-Options.
* -m11/60:                               PDP-11-Options.
* -m11/70:                               PDP-11-Options.
* -m11/73:                               PDP-11-Options.
* -m11/83:                               PDP-11-Options.
* -m11/84:                               PDP-11-Options.
* -m11/93:                               PDP-11-Options.
* -m11/94:                               PDP-11-Options.
* -m32r option, M32R:                    M32R-Opts.
* -m32rx option, M32RX:                  M32R-Opts.
* -m68000 and related options:           M68K-Opts.
* -m68hc11:                              M68HC11-Opts.
* -m68hc12:                              M68HC11-Opts.
* -mall:                                 PDP-11-Options.
* -mall-extensions:                      PDP-11-Options.
* -mapcs command line option, ARM:       ARM Options.
* -mapcs-float command line option, ARM: ARM Options.
* -mapcs-reentrant command line option, ARM: ARM Options.
* -marc[5|6|7|8] command line option, ARC: ARC Options.
* -march= command line option, ARM:      ARM Options.
* -matpcs command line option, ARM:      ARM Options.
* -mcis:                                 PDP-11-Options.
* -mCPU command line option, Alpha:      Alpha Options.
* -mcpu= command line option, ARM:       ARM Options.
* -mcsm:                                 PDP-11-Options.
* -mdebug command line option, Alpha:    Alpha Options.
* -meis:                                 PDP-11-Options.
* -mf11:                                 PDP-11-Options.
* -mfis:                                 PDP-11-Options.
* -mfp-11:                               PDP-11-Options.
* -mfpp:                                 PDP-11-Options.
* -mfpu:                                 PDP-11-Options.
* -mfpu= command line option, ARM:       ARM Options.
* -mj11:                                 PDP-11-Options.
* -mka11:                                PDP-11-Options.
* -mkb11:                                PDP-11-Options.
* -mkd11a:                               PDP-11-Options.
* -mkd11b:                               PDP-11-Options.
* -mkd11d:                               PDP-11-Options.
* -mkd11e:                               PDP-11-Options.
* -mkd11f:                               PDP-11-Options.
* -mkd11h:                               PDP-11-Options.
* -mkd11k:                               PDP-11-Options.
* -mkd11q:                               PDP-11-Options.
* -mkd11z:                               PDP-11-Options.
* -mkev11:                               PDP-11-Options.
* -mlimited-eis:                         PDP-11-Options.
* -mmfpt:                                PDP-11-Options.
* -mmicrocode:                           PDP-11-Options.
* -mmutiproc:                            PDP-11-Options.
* -mmxps:                                PDP-11-Options.
* -mno-cis:                              PDP-11-Options.
* -mno-csm:                              PDP-11-Options.
* -mno-eis:                              PDP-11-Options.
* -mno-extensions:                       PDP-11-Options.
* -mno-fis:                              PDP-11-Options.
* -mno-fp-11:                            PDP-11-Options.
* -mno-fpp:                              PDP-11-Options.
* -mno-fpu:                              PDP-11-Options.
* -mno-kev11:                            PDP-11-Options.
* -mno-limited-eis:                      PDP-11-Options.
* -mno-mfpt:                             PDP-11-Options.
* -mno-microcode:                        PDP-11-Options.
* -mno-mutiproc:                         PDP-11-Options.
* -mno-mxps:                             PDP-11-Options.
* -mno-pic:                              PDP-11-Options.
* -mno-spl:                              PDP-11-Options.
* -moabi command line option, ARM:       ARM Options.
* -mpic:                                 PDP-11-Options.
* -mspl:                                 PDP-11-Options.
* -mt11:                                 PDP-11-Options.
* -mthumb command line option, ARM:      ARM Options.
* -mthumb-interwork command line option, ARM: ARM Options.
* -mv850 command line option, V850:      V850 Options.
* -mv850any command line option, V850:   V850 Options.
* -mv850e command line option, V850:     V850 Options.
* -N command line option, CRIS:          CRIS-Opts.
* -no-construct-floats:                  MIPS Opts.
* -no-mdebug command line option, Alpha: Alpha Options.
* -no-relax option, i960:                Options-i960.
* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts.
* -nocpp ignored (MIPS):                 MIPS Opts.
* -o:                                    o.
* -R:                                    R.
* -relax:                                SH Options.
* -relax command line option, Alpha:     Alpha Options.
* -S, ignored on VAX:                    VAX-Opts.
* -small:                                SH Options.
* -t, ignored on VAX:                    VAX-Opts.
* -T, ignored on VAX:                    VAX-Opts.
* -v:                                    v.
* -V, redundant on VAX:                  VAX-Opts.
* -version:                              v.
* -W:                                    W.
* -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts.
* -Wnp option, M32RX:                    M32R-Opts.
* -Wp option, M32RX:                     M32R-Opts.
* -wsigned_overflow command line option, V850: V850 Options.
* -wunsigned_overflow command line option, V850: V850 Options.
* -x command line option, MMIX:          MMIX-Opts.
* . (symbol):                            Dot.
* .hidden directive:                     Hidden.
* .insn:                                 MIPS insn.
* .internal directive:                   Internal.
* .ltorg directive, ARM:                 ARM Directives.
* .o:                                    Object.
* .param on HPPA:                        HPPA Directives.
* .pool directive, ARM:                  ARM Directives.
* .popsection directive:                 PopSection.
* .previous directive:                   Previous.
* .protected directive:                  Protected.
* .pushsection directive:                PushSection.
* .set autoextend:                       MIPS autoextend.
* .set mdmx:                             MIPS ASE instruction generation overrides.
* .set mips3d:                           MIPS ASE instruction generation overrides.
* .set mipsN:                            MIPS ISA.
* .set noautoextend:                     MIPS autoextend.
* .set nomdmx:                           MIPS ASE instruction generation overrides.
* .set nomips3d:                         MIPS ASE instruction generation overrides.
* .set pop:                              MIPS option stack.
* .set push:                             MIPS option stack.
* .subsection directive:                 SubSection.
* .v850 directive, V850:                 V850 Directives.
* .v850e directive, V850:                V850 Directives.
* .version:                              Version.
* .vtable_entry:                         VTableEntry.
* .vtable_inherit:                       VTableInherit.
* .weak:                                 Weak.
* 16-bit code, i386:                     i386-16bit.
* 29K support:                           AMD29K-Dependent.
* 2byte directive, ARC:                  ARC Directives.
* 3byte directive, ARC:                  ARC Directives.
* 3DNow!, i386:                          i386-SIMD.
* 3DNow!, x86-64:                        i386-SIMD.
* 4byte directive, ARC:                  ARC Directives.
* : (label):                             Statements.
* @word modifier, D10V:                  D10V-Word.
* \" (doublequote character):            Strings.
* \\ (\ character):                      Strings.
* \b (backspace character):              Strings.
* \DDD (octal character code):           Strings.
* \f (formfeed character):               Strings.
* \n (newline character):                Strings.
* \r (carriage return character):        Strings.
* \t (tab):                              Strings.
* \XD... (hex character code):           Strings.
* a.out:                                 Object.
* a.out symbol attributes:               a.out Symbols.
* ABI options, SH64:                     SH64 Options.
* abort directive:                       Abort.
* ABORT directive:                       ABORT.
* absolute section:                      Ld Sections.
* addition, permitted arguments:         Infix Ops.
* addresses:                             Expressions.
* addresses, format of:                  Secs Background.
* addressing modes, D10V:                D10V-Addressing.
* addressing modes, D30V:                D30V-Addressing.
* addressing modes, H8/300:              H8/300-Addressing.
* addressing modes, H8/500:              H8/500-Addressing.
* addressing modes, M680x0:              M68K-Syntax.
* addressing modes, M68HC11:             M68HC11-Syntax.
* addressing modes, SH:                  SH-Addressing.
* addressing modes, SH64:                SH64-Addressing.
* addressing modes, Z8000:               Z8000-Addressing.
* ADR reg,<label> pseudo op, ARM:        ARM Opcodes.
* ADRL reg,<label> pseudo op, ARM:       ARM Opcodes.
* advancing location counter:            Org.
* align directive:                       Align.
* align directive, ARM:                  ARM Directives.
* align directive, M88K:                 M88K Directives.
* align directive, SPARC:                Sparc-Directives.
* Alpha floating point (IEEE):           Alpha Floating Point.
* Alpha line comment character:          Alpha-Chars.
* Alpha line separator:                  Alpha-Chars.
* Alpha notes:                           Alpha Notes.
* Alpha options:                         Alpha Options.
* Alpha registers:                       Alpha-Regs.
* Alpha relocations:                     Alpha-Relocs.
* Alpha support:                         Alpha-Dependent.
* Alpha Syntax:                          Alpha Options.
* Alpha-only directives:                 Alpha Directives.
* altered difference tables:             Word.
* alternate syntax for the 680x0:        M68K-Moto-Syntax.
* AMD 29K floating point (IEEE):         AMD29K Floating Point.
* AMD 29K identifiers:                   AMD29K-Chars.
* AMD 29K line comment character:        AMD29K-Chars.
* AMD 29K machine directives:            AMD29K Directives.
* AMD 29K macros:                        AMD29K-Macros.
* AMD 29K opcodes:                       AMD29K Opcodes.
* AMD 29K options (none):                AMD29K Options.
* AMD 29K protected registers:           AMD29K-Regs.
* AMD 29K register names:                AMD29K-Regs.
* AMD 29K special purpose registers:     AMD29K-Regs.
* AMD 29K support:                       AMD29K-Dependent.
* ARC floating point (IEEE):             ARC Floating Point.
* ARC machine directives:                ARC Directives.
* ARC opcodes:                           ARC Opcodes.
* ARC options (none):                    ARC Options.
* ARC register names:                    ARC-Regs.
* ARC special characters:                ARC-Chars.
* ARC support:                           ARC-Dependent.
* arc5 arc5, ARC:                        ARC Options.
* arc6 arc6, ARC:                        ARC Options.
* arc7 arc7, ARC:                        ARC Options.
* arc8 arc8, ARC:                        ARC Options.
* arch directive, i386:                  i386-Arch.
* arch directive, x86-64:                i386-Arch.
* architecture options, i960:            Options-i960.
* architecture options, M32R:            M32R-Opts.
* architecture options, M32RX:           M32R-Opts.
* architecture options, M680x0:          M68K-Opts.
* architectures, PowerPC:                PowerPC-Opts.
* architectures, SPARC:                  Sparc-Opts.
* arguments for addition:                Infix Ops.
* arguments for subtraction:             Infix Ops.
* arguments in expressions:              Arguments.
* arithmetic functions:                  Operators.
* arithmetic operands:                   Arguments.
* arm directive, ARM:                    ARM Directives.
* ARM floating point (IEEE):             ARM Floating Point.
* ARM identifiers:                       ARM-Chars.
* ARM immediate character:               ARM-Chars.
* ARM line comment character:            ARM-Chars.
* ARM line separator:                    ARM-Chars.
* ARM machine directives:                ARM Directives.
* ARM opcodes:                           ARM Opcodes.
* ARM options (none):                    ARM Options.
* ARM register names:                    ARM-Regs.
* ARM support:                           ARM-Dependent.
* ascii directive:                       Ascii.
* asciz directive:                       Asciz.
* assembler bugs, reporting:             Bug Reporting.
* assembler crash:                       Bug Criteria.
* assembler directive .dword, CRIS:      CRIS-Pseudos.
* assembler directive .syntax, CRIS:     CRIS-Pseudos.
* assembler directive BSPEC, MMIX:       MMIX-Pseudos.
* assembler directive BYTE, MMIX:        MMIX-Pseudos.
* assembler directive ESPEC, MMIX:       MMIX-Pseudos.
* assembler directive GREG, MMIX:        MMIX-Pseudos.
* assembler directive IS, MMIX:          MMIX-Pseudos.
* assembler directive LOC, MMIX:         MMIX-Pseudos.
* assembler directive LOCAL, MMIX:       MMIX-Pseudos.
* assembler directive OCTA, MMIX:        MMIX-Pseudos.
* assembler directive PREFIX, MMIX:      MMIX-Pseudos.
* assembler directive TETRA, MMIX:       MMIX-Pseudos.
* assembler directive WYDE, MMIX:        MMIX-Pseudos.
* assembler directives, CRIS:            CRIS-Pseudos.
* assembler directives, MMIX:            MMIX-Pseudos.
* assembler internal logic error:        As Sections.
* assembler version:                     v.
* assembler, and linker:                 Secs Background.
* assembly listings, enabling:           a.
* assigning values to symbols <1>:       Equ.
* assigning values to symbols:           Setting Symbols.
* atmp directive, i860:                  Directives-i860.
* att_syntax pseudo op, i386:            i386-Syntax.
* att_syntax pseudo op, x86-64:          i386-Syntax.
* attributes, symbol:                    Symbol Attributes.
* auxiliary attributes, COFF symbols:    COFF Symbols.
* auxiliary symbol information, COFF:    Dim.
* Av7:                                   Sparc-Opts.
* backslash (\\):                        Strings.
* backspace (\b):                        Strings.
* balign directive:                      Balign.
* balignl directive:                     Balign.
* balignw directive:                     Balign.
* big endian output, MIPS:               Overview.
* big endian output, PJ:                 Overview.
* big-endian output, MIPS:               MIPS Opts.
* bignums:                               Bignums.
* binary files, including:               Incbin.
* binary integers:                       Integers.
* bitfields, not supported on VAX:       VAX-no.
* block:                                 Z8000 Directives.
* block directive, AMD 29K:              AMD29K Directives.
* branch improvement, M680x0:            M68K-Branch.
* branch improvement, M68HC11:           M68HC11-Branch.
* branch improvement, VAX:               VAX-branch.
* branch recording, i960:                Options-i960.
* branch statistics table, i960:         Options-i960.
* BSD syntax:                            PDP-11-Syntax.
* bss directive, i960:                   Directives-i960.
* bss directive, M88K:                   M88K Directives.
* bss section <1>:                       bss.
* bss section:                           Ld Sections.
* bug criteria:                          Bug Criteria.
* bug reports:                           Bug Reporting.
* bugs in assembler:                     Reporting Bugs.
* bus lock prefixes, i386:               i386-Prefixes.
* bval:                                  Z8000 Directives.
* byte directive:                        Byte.
* call instructions, i386:               i386-Mnemonics.
* call instructions, x86-64:             i386-Mnemonics.
* callj, i960 pseudo-opcode:             callj-i960.
* carriage return (\r):                  Strings.
* character constants:                   Characters.
* character escape codes:                Strings.
* character, single:                     Chars.
* characters used in symbols:            Symbol Intro.
* code directive, ARM:                   ARM Directives.
* code16 directive, i386:                i386-16bit.
* code16gcc directive, i386:             i386-16bit.
* code32 directive, i386:                i386-16bit.
* code64 directive, i386:                i386-16bit.
* code64 directive, x86-64:              i386-16bit.
* COFF auxiliary symbol information:     Dim.
* COFF structure debugging:              Tag.
* COFF symbol attributes:                COFF Symbols.
* COFF symbol descriptor:                Desc.
* COFF symbol storage class:             Scl.
* COFF symbol type:                      Type.
* COFF symbols, debugging:               Def.
* COFF value attribute:                  Val.
* COMDAT:                                Linkonce.
* comm directive:                        Comm.
* command line conventions:              Command Line.
* command line options, V850:            V850 Options.
* command-line options ignored, VAX:     VAX-Opts.
* comments:                              Comments.
* comments, M680x0:                      M68K-Chars.
* comments, removed by preprocessor:     Preprocessing.
* common directive, SPARC:               Sparc-Directives.
* common sections:                       Linkonce.
* common variable storage:               bss.
* compare and jump expansions, i960:     Compare-and-branch-i960.
* compare/branch instructions, i960:     Compare-and-branch-i960.
* comparison expressions:                Infix Ops.
* conditional assembly:                  If.
* constant, single character:            Chars.
* constants:                             Constants.
* constants, bignum:                     Bignums.
* constants, character:                  Characters.
* constants, converted by preprocessor:  Preprocessing.
* constants, floating point:             Flonums.
* constants, integer:                    Integers.
* constants, number:                     Numbers.
* constants, string:                     Strings.
* conversion instructions, i386:         i386-Mnemonics.
* conversion instructions, x86-64:       i386-Mnemonics.
* coprocessor wait, i386:                i386-Prefixes.
* cputype directive, AMD 29K:            AMD29K Directives.
* crash of assembler:                    Bug Criteria.
* CRIS --emulation=crisaout command line option: CRIS-Opts.
* CRIS --emulation=criself command line option: CRIS-Opts.
* CRIS --no-underscore command line option: CRIS-Opts.
* CRIS --pic command line option:        CRIS-Opts.
* CRIS --underscore command line option: CRIS-Opts.
* CRIS -N command line option:           CRIS-Opts.
* CRIS assembler directive .dword:       CRIS-Pseudos.
* CRIS assembler directive .syntax:      CRIS-Pseudos.
* CRIS assembler directives:             CRIS-Pseudos.
* CRIS instruction expansion:            CRIS-Expand.
* CRIS line comment characters:          CRIS-Chars.
* CRIS options:                          CRIS-Opts.
* CRIS position-independent code:        CRIS-Opts.
* CRIS pseudo-op .dword:                 CRIS-Pseudos.
* CRIS pseudo-op .syntax:                CRIS-Pseudos.
* CRIS pseudo-ops:                       CRIS-Pseudos.
* CRIS register names:                   CRIS-Regs.
* CRIS support:                          CRIS-Dependent.
* CRIS symbols in position-independent code: CRIS-Pic.
* ctbp register, V850:                   V850-Regs.
* ctoff pseudo-op, V850:                 V850 Opcodes.
* ctpc register, V850:                   V850-Regs.
* ctpsw register, V850:                  V850-Regs.
* current address:                       Dot.
* current address, advancing:            Org.
* D10V @word modifier:                   D10V-Word.
* D10V addressing modes:                 D10V-Addressing.
* D10V floating point:                   D10V-Float.
* D10V line comment character:           D10V-Chars.
* D10V opcode summary:                   D10V-Opcodes.
* D10V optimization:                     Overview.
* D10V options:                          D10V-Opts.
* D10V registers:                        D10V-Regs.
* D10V size modifiers:                   D10V-Size.
* D10V sub-instruction ordering:         D10V-Chars.
* D10V sub-instructions:                 D10V-Subs.
* D10V support:                          D10V-Dependent.
* D10V syntax:                           D10V-Syntax.
* D30V addressing modes:                 D30V-Addressing.
* D30V floating point:                   D30V-Float.
* D30V Guarded Execution:                D30V-Guarded.
* D30V line comment character:           D30V-Chars.
* D30V nops:                             Overview.
* D30V nops after 32-bit multiply:       Overview.
* D30V opcode summary:                   D30V-Opcodes.
* D30V optimization:                     Overview.
* D30V options:                          D30V-Opts.
* D30V registers:                        D30V-Regs.
* D30V size modifiers:                   D30V-Size.
* D30V sub-instruction ordering:         D30V-Chars.
* D30V sub-instructions:                 D30V-Subs.
* D30V support:                          D30V-Dependent.
* D30V syntax:                           D30V-Syntax.
* data alignment on SPARC:               Sparc-Aligned-Data.
* data and text sections, joining:       R.
* data directive:                        Data.
* data section:                          Ld Sections.
* data1 directive, M680x0:               M68K-Directives.
* data2 directive, M680x0:               M68K-Directives.
* datalabel, SH64:                       SH64-Addressing.
* dbpc register, V850:                   V850-Regs.
* dbpsw register, V850:                  V850-Regs.
* debuggers, and symbol order:           Symbols.
* debugging COFF symbols:                Def.
* DEC syntax:                            PDP-11-Syntax.
* decimal integers:                      Integers.
* def directive:                         Def.
* def directive, M88K:                   M88K Directives.
* dependency tracking:                   MD.
* deprecated directives:                 Deprecated.
* desc directive:                        Desc.
* descriptor, of a.out symbol:           Symbol Desc.
* dfloat directive, M88K:                M88K Directives.
* dfloat directive, VAX:                 VAX-directives.
* difference tables altered:             Word.
* difference tables, warning:            K.
* differences, mmixal:                   MMIX-mmixal.
* dim directive:                         Dim.
* directives and instructions:           Statements.
* directives, M680x0:                    M68K-Directives.
* directives, machine independent:       Pseudo Ops.
* directives, Z8000:                     Z8000 Directives.
* displacement sizing character, VAX:    VAX-operands.
* dollar local symbols:                  Symbol Names.
* dot (symbol):                          Dot.
* double directive:                      Double.
* double directive, i386:                i386-Float.
* double directive, M680x0:              M68K-Float.
* double directive, M68HC11:             M68HC11-Float.
* double directive, VAX:                 VAX-float.
* double directive, x86-64:              i386-Float.
* doublequote (\"):                      Strings.
* dual directive, i860:                  Directives-i860.
* ECOFF sections:                        MIPS Object.
* ecr register, V850:                    V850-Regs.
* eight-byte integer:                    Quad.
* eipc register, V850:                   V850-Regs.
* eipsw register, V850:                  V850-Regs.
* eject directive:                       Eject.
* ELF symbol type:                       Type.
* else directive:                        Else.
* elseif directive:                      Elseif.
* empty expressions:                     Empty Exprs.
* emulation:                             Overview.
* end directive:                         End.
* enddual directive, i860:               Directives-i860.
* endef directive:                       Endef.
* endfunc directive:                     Endfunc.
* endianness, MIPS:                      Overview.
* endianness, PJ:                        Overview.
* endif directive:                       Endif.
* endm directive:                        Macro.
* EOF, newline must precede:             Statements.
* ep register, V850:                     V850-Regs.
* equ directive:                         Equ.
* equiv directive:                       Equiv.
* err directive:                         Err.
* error messages:                        Errors.
* error on valid input:                  Bug Criteria.
* errors, caused by warnings:            W.
* errors, continuing after:              Z.
* ESA/390 floating point (IEEE):         ESA/390 Floating Point.
* ESA/390 support:                       ESA/390-Dependent.
* ESA/390 Syntax:                        ESA/390 Options.
* ESA/390-only directives:               ESA/390 Directives.
* escape codes, character:               Strings.
* even:                                  Z8000 Directives.
* even directive, M680x0:                M68K-Directives.
* exitm directive:                       Macro.
* expr (internal section):               As Sections.
* expression arguments:                  Arguments.
* expressions:                           Expressions.
* expressions, comparison:               Infix Ops.
* expressions, empty:                    Empty Exprs.
* expressions, integer:                  Integer Exprs.
* extAuxRegister directive, ARC:         ARC Directives.
* extCondCode directive, ARC:            ARC Directives.
* extCoreRegister directive, ARC:        ARC Directives.
* extend directive M680x0:               M68K-Float.
* extend directive M68HC11:              M68HC11-Float.
* extended directive, i960:              Directives-i960.
* extern directive:                      Extern.
* extInstruction directive, ARC:         ARC Directives.
* fail directive:                        Fail.
* faster processing (-f):                f.
* fatal signal:                          Bug Criteria.
* fepc register, V850:                   V850-Regs.
* fepsw register, V850:                  V850-Regs.
* ffloat directive, M88K:                M88K Directives.
* ffloat directive, VAX:                 VAX-directives.
* file directive:                        File.
* file directive, AMD 29K:               AMD29K Directives.
* file name, logical:                    File.
* files, including:                      Include.
* files, input:                          Input Files.
* fill directive:                        Fill.
* filling memory <1>:                    Skip.
* filling memory:                        Space.
* float directive:                       Float.
* float directive, i386:                 i386-Float.
* float directive, M680x0:               M68K-Float.
* float directive, M68HC11:              M68HC11-Float.
* float directive, VAX:                  VAX-float.
* float directive, x86-64:               i386-Float.
* floating point numbers:                Flonums.
* floating point numbers (double):       Double.
* floating point numbers (single) <1>:   Single.
* floating point numbers (single):       Float.
* floating point, Alpha (IEEE):          Alpha Floating Point.
* floating point, AMD 29K (IEEE):        AMD29K Floating Point.
* floating point, ARC (IEEE):            ARC Floating Point.
* floating point, ARM (IEEE):            ARM Floating Point.
* floating point, D10V:                  D10V-Float.
* floating point, D30V:                  D30V-Float.
* floating point, ESA/390 (IEEE):        ESA/390 Floating Point.
* floating point, H8/300 (IEEE):         H8/300 Floating Point.
* floating point, H8/500 (IEEE):         H8/500 Floating Point.
* floating point, HPPA (IEEE):           HPPA Floating Point.
* floating point, i386:                  i386-Float.
* floating point, i960 (IEEE):           Floating Point-i960.
* floating point, M680x0:                M68K-Float.
* floating point, M68HC11:               M68HC11-Float.
* floating point, SH (IEEE):             SH Floating Point.
* floating point, SPARC (IEEE):          Sparc-Float.
* floating point, V850 (IEEE):           V850 Floating Point.
* floating point, VAX:                   VAX-float.
* floating point, x86-64:                i386-Float.
* flonums:                               Flonums.
* force_thumb directive, ARM:            ARM Directives.
* format of error messages:              Errors.
* format of warning messages:            Errors.
* formfeed (\f):                         Strings.
* func directive:                        Func.
* functions, in expressions:             Operators.
* gbr960, i960 postprocessor:            Options-i960.
* gfloat directive, VAX:                 VAX-directives.
* global:                                Z8000 Directives.
* global directive:                      Global.
* gp register, MIPS:                     MIPS Object.
* gp register, V850:                     V850-Regs.
* grouping data:                         Sub-Sections.
* H8/300 addressing modes:               H8/300-Addressing.
* H8/300 floating point (IEEE):          H8/300 Floating Point.
* H8/300 line comment character:         H8/300-Chars.
* H8/300 line separator:                 H8/300-Chars.
* H8/300 machine directives (none):      H8/300 Directives.
* H8/300 opcode summary:                 H8/300 Opcodes.
* H8/300 options (none):                 H8/300 Options.
* H8/300 registers:                      H8/300-Regs.
* H8/300 size suffixes:                  H8/300 Opcodes.
* H8/300 support:                        H8/300-Dependent.
* H8/300H, assembling for:               H8/300 Directives.
* H8/500 addressing modes:               H8/500-Addressing.
* H8/500 floating point (IEEE):          H8/500 Floating Point.
* H8/500 line comment character:         H8/500-Chars.
* H8/500 line separator:                 H8/500-Chars.
* H8/500 machine directives (none):      H8/500 Directives.
* H8/500 opcode summary:                 H8/500 Opcodes.
* H8/500 options (none):                 H8/500 Options.
* H8/500 registers:                      H8/500-Regs.
* H8/500 support:                        H8/500-Dependent.
* half directive, ARC:                   ARC Directives.
* half directive, M88K:                  M88K Directives.
* half directive, SPARC:                 Sparc-Directives.
* hex character code (\XD...):           Strings.
* hexadecimal integers:                  Integers.
* hfloat directive, VAX:                 VAX-directives.
* hi pseudo-op, V850:                    V850 Opcodes.
* hi0 pseudo-op, V850:                   V850 Opcodes.
* hilo pseudo-op, V850:                  V850 Opcodes.
* HPPA directives not supported:         HPPA Directives.
* HPPA floating point (IEEE):            HPPA Floating Point.
* HPPA Syntax:                           HPPA Options.
* HPPA-only directives:                  HPPA Directives.
* hword directive:                       hword.
* i370 support:                          ESA/390-Dependent.
* i386 16-bit code:                      i386-16bit.
* i386 arch directive:                   i386-Arch.
* i386 att_syntax pseudo op:             i386-Syntax.
* i386 conversion instructions:          i386-Mnemonics.
* i386 floating point:                   i386-Float.
* i386 immediate operands:               i386-Syntax.
* i386 instruction naming:               i386-Mnemonics.
* i386 instruction prefixes:             i386-Prefixes.
* i386 intel_syntax pseudo op:           i386-Syntax.
* i386 jump optimization:                i386-Jumps.
* i386 jump, call, return:               i386-Syntax.
* i386 jump/call operands:               i386-Syntax.
* i386 memory references:                i386-Memory.
* i386 mul, imul instructions:           i386-Notes.
* i386 options:                          i386-Options.
* i386 register operands:                i386-Syntax.
* i386 registers:                        i386-Regs.
* i386 sections:                         i386-Syntax.
* i386 size suffixes:                    i386-Syntax.
* i386 source, destination operands:     i386-Syntax.
* i386 support:                          i386-Dependent.
* i386 syntax compatibility:             i386-Syntax.
* i80306 support:                        i386-Dependent.
* i860 machine directives:               Directives-i860.
* i860 opcodes:                          Opcodes for i860.
* i860 support:                          i860-Dependent.
* i960 architecture options:             Options-i960.
* i960 branch recording:                 Options-i960.
* i960 callj pseudo-opcode:              callj-i960.
* i960 compare and jump expansions:      Compare-and-branch-i960.
* i960 compare/branch instructions:      Compare-and-branch-i960.
* i960 floating point (IEEE):            Floating Point-i960.
* i960 machine directives:               Directives-i960.
* i960 opcodes:                          Opcodes for i960.
* i960 options:                          Options-i960.
* i960 support:                          i960-Dependent.
* ident directive:                       Ident.
* identifiers, AMD 29K:                  AMD29K-Chars.
* identifiers, ARM:                      ARM-Chars.
* if directive:                          If.
* ifc directive:                         If.
* ifdef directive:                       If.
* ifeq directive:                        If.
* ifeqs directive:                       If.
* ifge directive:                        If.
* ifgt directive:                        If.
* ifle directive:                        If.
* iflt directive:                        If.
* ifnc directive:                        If.
* ifndef directive:                      If.
* ifne directive:                        If.
* ifnes directive:                       If.
* ifnotdef directive:                    If.
* immediate character, ARM:              ARM-Chars.
* immediate character, M680x0:           M68K-Chars.
* immediate character, VAX:              VAX-operands.
* immediate operands, i386:              i386-Syntax.
* immediate operands, x86-64:            i386-Syntax.
* imul instruction, i386:                i386-Notes.
* imul instruction, x86-64:              i386-Notes.
* incbin directive:                      Incbin.
* include directive:                     Include.
* include directive search path:         I.
* indirect character, VAX:               VAX-operands.
* infix operators:                       Infix Ops.
* inhibiting interrupts, i386:           i386-Prefixes.
* input:                                 Input Files.
* input file linenumbers:                Input Files.
* instruction expansion, CRIS:           CRIS-Expand.
* instruction expansion, MMIX:           MMIX-Expand.
* instruction naming, i386:              i386-Mnemonics.
* instruction naming, x86-64:            i386-Mnemonics.
* instruction prefixes, i386:            i386-Prefixes.
* instruction set, M680x0:               M68K-opcodes.
* instruction set, M68HC11:              M68HC11-opcodes.
* instruction summary, D10V:             D10V-Opcodes.
* instruction summary, D30V:             D30V-Opcodes.
* instruction summary, H8/300:           H8/300 Opcodes.
* instruction summary, H8/500:           H8/500 Opcodes.
* instruction summary, SH:               SH Opcodes.
* instruction summary, SH64:             SH64 Opcodes.
* instruction summary, Z8000:            Z8000 Opcodes.
* instructions and directives:           Statements.
* int directive:                         Int.
* int directive, H8/300:                 H8/300 Directives.
* int directive, H8/500:                 H8/500 Directives.
* int directive, i386:                   i386-Float.
* int directive, x86-64:                 i386-Float.
* integer expressions:                   Integer Exprs.
* integer, 16-byte:                      Octa.
* integer, 8-byte:                       Quad.
* integers:                              Integers.
* integers, 16-bit:                      hword.
* integers, 32-bit:                      Int.
* integers, binary:                      Integers.
* integers, decimal:                     Integers.
* integers, hexadecimal:                 Integers.
* integers, octal:                       Integers.
* integers, one byte:                    Byte.
* intel_syntax pseudo op, i386:          i386-Syntax.
* intel_syntax pseudo op, x86-64:        i386-Syntax.
* internal assembler sections:           As Sections.
* invalid input:                         Bug Criteria.
* invocation summary:                    Overview.
* irp directive:                         Irp.
* irpc directive:                        Irpc.
* ISA options, SH64:                     SH64 Options.
* joining text and data sections:        R.
* jump instructions, i386:               i386-Mnemonics.
* jump instructions, x86-64:             i386-Mnemonics.
* jump optimization, i386:               i386-Jumps.
* jump optimization, x86-64:             i386-Jumps.
* jump/call operands, i386:              i386-Syntax.
* jump/call operands, x86-64:            i386-Syntax.
* label (:):                             Statements.
* labels:                                Labels.
* lcomm directive:                       Lcomm.
* ld:                                    Object.
* ldouble directive M680x0:              M68K-Float.
* ldouble directive M68HC11:             M68HC11-Float.
* LDR reg,=<label> pseudo op, ARM:       ARM Opcodes.
* leafproc directive, i960:              Directives-i960.
* length of symbols:                     Symbol Intro.
* lflags directive (ignored):            Lflags.
* line comment character:                Comments.
* line comment character, Alpha:         Alpha-Chars.
* line comment character, AMD 29K:       AMD29K-Chars.
* line comment character, ARM:           ARM-Chars.
* line comment character, D10V:          D10V-Chars.
* line comment character, D30V:          D30V-Chars.
* line comment character, H8/300:        H8/300-Chars.
* line comment character, H8/500:        H8/500-Chars.
* line comment character, M680x0:        M68K-Chars.
* line comment character, SH:            SH-Chars.
* line comment character, SH64:          SH64-Chars.
* line comment character, V850:          V850-Chars.
* line comment character, Z8000:         Z8000-Chars.
* line comment characters, CRIS:         CRIS-Chars.
* line comment characters, MMIX:         MMIX-Chars.
* line directive:                        Line.
* line directive, AMD 29K:               AMD29K Directives.
* line numbers, in input files:          Input Files.
* line numbers, in warnings/errors:      Errors.
* line separator character:              Statements.
* line separator, Alpha:                 Alpha-Chars.
* line separator, ARM:                   ARM-Chars.
* line separator, H8/300:                H8/300-Chars.
* line separator, H8/500:                H8/500-Chars.
* line separator, SH:                    SH-Chars.
* line separator, SH64:                  SH64-Chars.
* line separator, Z8000:                 Z8000-Chars.
* lines starting with #:                 Comments.
* linker:                                Object.
* linker, and assembler:                 Secs Background.
* linkonce directive:                    Linkonce.
* list directive:                        List.
* listing control, turning off:          Nolist.
* listing control, turning on:           List.
* listing control: new page:             Eject.
* listing control: paper size:           Psize.
* listing control: subtitle:             Sbttl.
* listing control: title line:           Title.
* listings, enabling:                    a.
* little endian output, MIPS:            Overview.
* little endian output, PJ:              Overview.
* little-endian output, MIPS:            MIPS Opts.
* ln directive:                          Ln.
* lo pseudo-op, V850:                    V850 Opcodes.
* local common symbols:                  Lcomm.
* local labels, retaining in output:     L.
* local symbol names:                    Symbol Names.
* location counter:                      Dot.
* location counter, advancing:           Org.
* logical file name:                     File.
* logical line number:                   Line.
* logical line numbers:                  Comments.
* long directive:                        Long.
* long directive, ARC:                   ARC Directives.
* long directive, i386:                  i386-Float.
* long directive, x86-64:                i386-Float.
* lp register, V850:                     V850-Regs.
* lval:                                  Z8000 Directives.
* M32R architecture options:             M32R-Opts.
* M32R options:                          M32R-Opts.
* M32R support:                          M32R-Dependent.
* M32R warnings:                         M32R-Warnings.
* M680x0 addressing modes:               M68K-Syntax.
* M680x0 architecture options:           M68K-Opts.
* M680x0 branch improvement:             M68K-Branch.
* M680x0 directives:                     M68K-Directives.
* M680x0 floating point:                 M68K-Float.
* M680x0 immediate character:            M68K-Chars.
* M680x0 line comment character:         M68K-Chars.
* M680x0 opcodes:                        M68K-opcodes.
* M680x0 options:                        M68K-Opts.
* M680x0 pseudo-opcodes:                 M68K-Branch.
* M680x0 size modifiers:                 M68K-Syntax.
* M680x0 support:                        M68K-Dependent.
* M680x0 syntax:                         M68K-Syntax.
* M68HC11 addressing modes:              M68HC11-Syntax.
* M68HC11 and M68HC12 support:           M68HC11-Dependent.
* M68HC11 branch improvement:            M68HC11-Branch.
* M68HC11 floating point:                M68HC11-Float.
* M68HC11 opcodes:                       M68HC11-opcodes.
* M68HC11 options:                       M68HC11-Opts.
* M68HC11 pseudo-opcodes:                M68HC11-Branch.
* M68HC11 syntax:                        M68HC11-Syntax.
* M88K support:                          M88K-Dependent.
* machine dependencies:                  Machine Dependencies.
* machine directives, AMD 29K:           AMD29K Directives.
* machine directives, ARC:               ARC Directives.
* machine directives, ARM:               ARM Directives.
* machine directives, H8/300 (none):     H8/300 Directives.
* machine directives, H8/500 (none):     H8/500 Directives.
* machine directives, i860:              Directives-i860.
* machine directives, i960:              Directives-i960.
* machine directives, SH:                SH Directives.
* machine directives, SH64:              SH64 Directives.
* machine directives, SPARC:             Sparc-Directives.
* machine directives, V850:              V850 Directives.
* machine directives, VAX:               VAX-directives.
* machine independent directives:        Pseudo Ops.
* machine instructions (not covered):    Manual.
* machine-independent syntax:            Syntax.
* macro directive:                       Macro.
* macros:                                Macro.
* Macros, AMD 29K:                       AMD29K-Macros.
* macros, count executed:                Macro.
* make rules:                            MD.
* manual, structure and purpose:         Manual.
* Maximum number of continuation lines:  listing.
* memory references, i386:               i386-Memory.
* memory references, x86-64:             i386-Memory.
* merging text and data sections:        R.
* messages from assembler:               Errors.
* minus, permitted arguments:            Infix Ops.
* MIPS architecture options:             MIPS Opts.
* MIPS big-endian output:                MIPS Opts.
* MIPS debugging directives:             MIPS Stabs.
* MIPS ECOFF sections:                   MIPS Object.
* MIPS endianness:                       Overview.
* MIPS ISA:                              Overview.
* MIPS ISA override:                     MIPS ISA.
* MIPS little-endian output:             MIPS Opts.
* MIPS MDMX instruction generation override: MIPS ASE instruction generation overrides.
* MIPS MIPS-3D instruction generation override: MIPS ASE instruction generation overrides.
* MIPS option stack:                     MIPS option stack.
* MIPS processor:                        MIPS-Dependent.
* MIT:                                   M68K-Syntax.
* MMIX assembler directive BSPEC:        MMIX-Pseudos.
* MMIX assembler directive BYTE:         MMIX-Pseudos.
* MMIX assembler directive ESPEC:        MMIX-Pseudos.
* MMIX assembler directive GREG:         MMIX-Pseudos.
* MMIX assembler directive IS:           MMIX-Pseudos.
* MMIX assembler directive LOC:          MMIX-Pseudos.
* MMIX assembler directive LOCAL:        MMIX-Pseudos.
* MMIX assembler directive OCTA:         MMIX-Pseudos.
* MMIX assembler directive PREFIX:       MMIX-Pseudos.
* MMIX assembler directive TETRA:        MMIX-Pseudos.
* MMIX assembler directive WYDE:         MMIX-Pseudos.
* MMIX assembler directives:             MMIX-Pseudos.
* MMIX line comment characters:          MMIX-Chars.
* MMIX options:                          MMIX-Opts.
* MMIX pseudo-op BSPEC:                  MMIX-Pseudos.
* MMIX pseudo-op BYTE:                   MMIX-Pseudos.
* MMIX pseudo-op ESPEC:                  MMIX-Pseudos.
* MMIX pseudo-op GREG:                   MMIX-Pseudos.
* MMIX pseudo-op IS:                     MMIX-Pseudos.
* MMIX pseudo-op LOC:                    MMIX-Pseudos.
* MMIX pseudo-op LOCAL:                  MMIX-Pseudos.
* MMIX pseudo-op OCTA:                   MMIX-Pseudos.
* MMIX pseudo-op PREFIX:                 MMIX-Pseudos.
* MMIX pseudo-op TETRA:                  MMIX-Pseudos.
* MMIX pseudo-op WYDE:                   MMIX-Pseudos.
* MMIX pseudo-ops:                       MMIX-Pseudos.
* MMIX register names:                   MMIX-Regs.
* MMIX support:                          MMIX-Dependent.
* mmixal differences:                    MMIX-mmixal.
* MMX, i386:                             i386-SIMD.
* MMX, x86-64:                           i386-SIMD.
* mnemonic suffixes, i386:               i386-Syntax.
* mnemonic suffixes, x86-64:             i386-Syntax.
* mnemonics for opcodes, VAX:            VAX-opcodes.
* mnemonics, D10V:                       D10V-Opcodes.
* mnemonics, D30V:                       D30V-Opcodes.
* mnemonics, H8/300:                     H8/300 Opcodes.
* mnemonics, H8/500:                     H8/500 Opcodes.
* mnemonics, SH:                         SH Opcodes.
* mnemonics, SH64:                       SH64 Opcodes.
* mnemonics, Z8000:                      Z8000 Opcodes.
* Motorola syntax for the 680x0:         M68K-Moto-Syntax.
* MRI compatibility mode:                M.
* mri directive:                         MRI.
* MRI mode, temporarily:                 MRI.
* mul instruction, i386:                 i386-Notes.
* mul instruction, x86-64:               i386-Notes.
* name:                                  Z8000 Directives.
* named section:                         Section.
* named sections:                        Ld Sections.
* names, symbol:                         Symbol Names.
* naming object file:                    o.
* new page, in listings:                 Eject.
* newline (\n):                          Strings.
* newline, required at file end:         Statements.
* nolist directive:                      Nolist.
* NOP pseudo op, ARM:                    ARM Opcodes.
* notes for Alpha:                       Alpha Notes.
* null-terminated strings:               Asciz.
* number constants:                      Numbers.
* number of macros executed:             Macro.
* numbered subsections:                  Sub-Sections.
* numbers, 16-bit:                       hword.
* numeric values:                        Expressions.
* nword directive, SPARC:                Sparc-Directives.
* object file:                           Object.
* object file format:                    Object Formats.
* object file name:                      o.
* object file, after errors:             Z.
* obsolescent directives:                Deprecated.
* octa directive:                        Octa.
* octal character code (\DDD):           Strings.
* octal integers:                        Integers.
* offset directive, V850:                V850 Directives.
* opcode mnemonics, VAX:                 VAX-opcodes.
* opcode summary, D10V:                  D10V-Opcodes.
* opcode summary, D30V:                  D30V-Opcodes.
* opcode summary, H8/300:                H8/300 Opcodes.
* opcode summary, H8/500:                H8/500 Opcodes.
* opcode summary, SH:                    SH Opcodes.
* opcode summary, SH64:                  SH64 Opcodes.
* opcode summary, Z8000:                 Z8000 Opcodes.
* opcodes for AMD 29K:                   AMD29K Opcodes.
* opcodes for ARC:                       ARC Opcodes.
* opcodes for ARM:                       ARM Opcodes.
* opcodes for V850:                      V850 Opcodes.
* opcodes, i860:                         Opcodes for i860.
* opcodes, i960:                         Opcodes for i960.
* opcodes, M680x0:                       M68K-opcodes.
* opcodes, M68HC11:                      M68HC11-opcodes.
* operand delimiters, i386:              i386-Syntax.
* operand delimiters, x86-64:            i386-Syntax.
* operand notation, VAX:                 VAX-operands.
* operands in expressions:               Arguments.
* operator precedence:                   Infix Ops.
* operators, in expressions:             Operators.
* operators, permitted arguments:        Infix Ops.
* optimization, D10V:                    Overview.
* optimization, D30V:                    Overview.
* option directive, ARC:                 ARC Directives.
* option summary:                        Overview.
* options for Alpha:                     Alpha Options.
* options for AMD29K (none):             AMD29K Options.
* options for ARC (none):                ARC Options.
* options for ARM (none):                ARM Options.
* options for i386:                      i386-Options.
* options for PDP-11:                    PDP-11-Options.
* options for PowerPC:                   PowerPC-Opts.
* options for SPARC:                     Sparc-Opts.
* options for V850 (none):               V850 Options.
* options for VAX/VMS:                   VAX-Opts.
* options for x86-64:                    i386-Options.
* options, all versions of assembler:    Invoking.
* options, command line:                 Command Line.
* options, CRIS:                         CRIS-Opts.
* options, D10V:                         D10V-Opts.
* options, D30V:                         D30V-Opts.
* options, H8/300 (none):                H8/300 Options.
* options, H8/500 (none):                H8/500 Options.
* options, i960:                         Options-i960.
* options, M32R:                         M32R-Opts.
* options, M680x0:                       M68K-Opts.
* options, M68HC11:                      M68HC11-Opts.
* options, MMIX:                         MMIX-Opts.
* options, PJ:                           PJ Options.
* options, SH:                           SH Options.
* options, SH64:                         SH64 Options.
* options, Z8000:                        Z8000 Options.
* org directive:                         Org.
* other attribute, of a.out symbol:      Symbol Other.
* output file:                           Object.
* p2align directive:                     P2align.
* p2alignl directive:                    P2align.
* p2alignw directive:                    P2align.
* padding the location counter:          Align.
* padding the location counter given a power of two: P2align.
* padding the location counter given number of bytes: Balign.
* page, in listings:                     Eject.
* paper size, for listings:              Psize.
* paths for .include:                    I.
* patterns, writing in memory:           Fill.
* PDP-11 comments:                       PDP-11-Syntax.
* PDP-11 floating-point register syntax: PDP-11-Syntax.
* PDP-11 general-purpose register syntax: PDP-11-Syntax.
* PDP-11 instruction naming:             PDP-11-Mnemonics.
* PDP-11 support:                        PDP-11-Dependent.
* PDP-11 syntax:                         PDP-11-Syntax.
* PIC code generation for ARM:           ARM Options.
* PJ endianness:                         Overview.
* PJ options:                            PJ Options.
* PJ support:                            PJ-Dependent.
* plus, permitted arguments:             Infix Ops.
* Position-independent code, CRIS:       CRIS-Opts.
* Position-independent code, symbols in, CRIS: CRIS-Pic.
* PowerPC architectures:                 PowerPC-Opts.
* PowerPC options:                       PowerPC-Opts.
* PowerPC support:                       PPC-Dependent.
* precedence of operators:               Infix Ops.
* precision, floating point:             Flonums.
* prefix operators:                      Prefix Ops.
* prefixes, i386:                        i386-Prefixes.
* preprocessing:                         Preprocessing.
* preprocessing, turning on and off:     Preprocessing.
* primary attributes, COFF symbols:      COFF Symbols.
* print directive:                       Print.
* proc directive, SPARC:                 Sparc-Directives.
* protected registers, AMD 29K:          AMD29K-Regs.
* pseudo-op .dword, CRIS:                CRIS-Pseudos.
* pseudo-op .syntax, CRIS:               CRIS-Pseudos.
* pseudo-op BSPEC, MMIX:                 MMIX-Pseudos.
* pseudo-op BYTE, MMIX:                  MMIX-Pseudos.
* pseudo-op ESPEC, MMIX:                 MMIX-Pseudos.
* pseudo-op GREG, MMIX:                  MMIX-Pseudos.
* pseudo-op IS, MMIX:                    MMIX-Pseudos.
* pseudo-op LOC, MMIX:                   MMIX-Pseudos.
* pseudo-op LOCAL, MMIX:                 MMIX-Pseudos.
* pseudo-op OCTA, MMIX:                  MMIX-Pseudos.
* pseudo-op PREFIX, MMIX:                MMIX-Pseudos.
* pseudo-op TETRA, MMIX:                 MMIX-Pseudos.
* pseudo-op WYDE, MMIX:                  MMIX-Pseudos.
* pseudo-opcodes, M680x0:                M68K-Branch.
* pseudo-opcodes, M68HC11:               M68HC11-Branch.
* pseudo-ops for branch, VAX:            VAX-branch.
* pseudo-ops, CRIS:                      CRIS-Pseudos.
* pseudo-ops, machine independent:       Pseudo Ops.
* pseudo-ops, MMIX:                      MMIX-Pseudos.
* psize directive:                       Psize.
* psw register, V850:                    V850-Regs.
* purgem directive:                      Purgem.
* purpose of GNU assembler:              GNU Assembler.
* quad directive:                        Quad.
* quad directive, i386:                  i386-Float.
* quad directive, x86-64:                i386-Float.
* real-mode code, i386:                  i386-16bit.
* register directive, SPARC:             Sparc-Directives.
* register names, Alpha:                 Alpha-Regs.
* register names, AMD 29K:               AMD29K-Regs.
* register names, ARC:                   ARC-Regs.
* register names, ARM:                   ARM-Regs.
* register names, CRIS:                  CRIS-Regs.
* register names, H8/300:                H8/300-Regs.
* register names, MMIX:                  MMIX-Regs.
* register names, V850:                  V850-Regs.
* register names, VAX:                   VAX-operands.
* register operands, i386:               i386-Syntax.
* register operands, x86-64:             i386-Syntax.
* registers, D10V:                       D10V-Regs.
* registers, D30V:                       D30V-Regs.
* registers, H8/500:                     H8/500-Regs.
* registers, i386:                       i386-Regs.
* registers, SH:                         SH-Regs.
* registers, SH64:                       SH64-Regs.
* registers, x86-64:                     i386-Regs.
* registers, Z8000:                      Z8000-Regs.
* relocation:                            Sections.
* relocation example:                    Ld Sections.
* relocations, Alpha:                    Alpha-Relocs.
* repeat prefixes, i386:                 i386-Prefixes.
* reporting bugs in assembler:           Reporting Bugs.
* rept directive:                        Rept.
* req directive, ARM:                    ARM Directives.
* reserve directive, SPARC:              Sparc-Directives.
* return instructions, i386:             i386-Syntax.
* return instructions, x86-64:           i386-Syntax.
* REX prefixes, i386:                    i386-Prefixes.
* rsect:                                 Z8000 Directives.
* sbttl directive:                       Sbttl.
* scl directive:                         Scl.
* sdaoff pseudo-op, V850:                V850 Opcodes.
* search path for .include:              I.
* sect directive, AMD 29K:               AMD29K Directives.
* section directive:                     Section.
* section directive, V850:               V850 Directives.
* section override prefixes, i386:       i386-Prefixes.
* Section Stack <1>:                     Previous.
* Section Stack <2>:                     PushSection.
* Section Stack <3>:                     Section.
* Section Stack <4>:                     PopSection.
* Section Stack:                         SubSection.
* section-relative addressing:           Secs Background.
* sections:                              Sections.
* sections in messages, internal:        As Sections.
* sections, i386:                        i386-Syntax.
* sections, named:                       Ld Sections.
* sections, x86-64:                      i386-Syntax.
* seg directive, SPARC:                  Sparc-Directives.
* segm:                                  Z8000 Directives.
* set directive:                         Set.
* set directive, M88K:                   M88K Directives.
* SH addressing modes:                   SH-Addressing.
* SH floating point (IEEE):              SH Floating Point.
* SH line comment character:             SH-Chars.
* SH line separator:                     SH-Chars.
* SH machine directives:                 SH Directives.
* SH opcode summary:                     SH Opcodes.
* SH options:                            SH Options.
* SH registers:                          SH-Regs.
* SH support:                            SH-Dependent.
* SH64 ABI options:                      SH64 Options.
* SH64 addressing modes:                 SH64-Addressing.
* SH64 ISA options:                      SH64 Options.
* SH64 line comment character:           SH64-Chars.
* SH64 line separator:                   SH64-Chars.
* SH64 machine directives:               SH64 Directives.
* SH64 opcode summary:                   SH64 Opcodes.
* SH64 options:                          SH64 Options.
* SH64 registers:                        SH64-Regs.
* SH64 support:                          SH64-Dependent.
* short directive:                       Short.
* short directive, ARC:                  ARC Directives.
* SIMD, i386:                            i386-SIMD.
* SIMD, x86-64:                          i386-SIMD.
* single character constant:             Chars.
* single directive:                      Single.
* single directive, i386:                i386-Float.
* single directive, x86-64:              i386-Float.
* sixteen bit integers:                  hword.
* sixteen byte integer:                  Octa.
* size directive:                        Size.
* size modifiers, D10V:                  D10V-Size.
* size modifiers, D30V:                  D30V-Size.
* size modifiers, M680x0:                M68K-Syntax.
* size prefixes, i386:                   i386-Prefixes.
* size suffixes, H8/300:                 H8/300 Opcodes.
* sizes operands, i386:                  i386-Syntax.
* sizes operands, x86-64:                i386-Syntax.
* skip directive:                        Skip.
* skip directive, M680x0:                M68K-Directives.
* skip directive, SPARC:                 Sparc-Directives.
* sleb128 directive:                     Sleb128.
* small objects, MIPS ECOFF:             MIPS Object.
* SOM symbol attributes:                 SOM Symbols.
* source program:                        Input Files.
* source, destination operands; i386:    i386-Syntax.
* source, destination operands; x86-64:  i386-Syntax.
* sp register, V850:                     V850-Regs.
* space directive:                       Space.
* space used, maximum for assembly:      statistics.
* SPARC architectures:                   Sparc-Opts.
* SPARC data alignment:                  Sparc-Aligned-Data.
* SPARC floating point (IEEE):           Sparc-Float.
* SPARC machine directives:              Sparc-Directives.
* SPARC options:                         Sparc-Opts.
* SPARC support:                         Sparc-Dependent.
* special characters, ARC:               ARC-Chars.
* special characters, M680x0:            M68K-Chars.
* special purpose registers, AMD 29K:    AMD29K-Regs.
* stabd directive:                       Stab.
* stabn directive:                       Stab.
* stabs directive:                       Stab.
* stabX directives:                      Stab.
* standard assembler sections:           Secs Background.
* standard input, as input file:         Command Line.
* statement separator character:         Statements.
* statement separator, Alpha:            Alpha-Chars.
* statement separator, ARM:              ARM-Chars.
* statement separator, H8/300:           H8/300-Chars.
* statement separator, H8/500:           H8/500-Chars.
* statement separator, SH:               SH-Chars.
* statement separator, SH64:             SH64-Chars.
* statement separator, Z8000:            Z8000-Chars.
* statements, structure of:              Statements.
* statistics, about assembly:            statistics.
* stopping the assembly:                 Abort.
* string constants:                      Strings.
* string directive:                      String.
* string directive on HPPA:              HPPA Directives.
* string directive, M88K:                M88K Directives.
* string literals:                       Ascii.
* string, copying to object file:        String.
* struct directive:                      Struct.
* structure debugging, COFF:             Tag.
* sub-instruction ordering, D10V:        D10V-Chars.
* sub-instruction ordering, D30V:        D30V-Chars.
* sub-instructions, D10V:                D10V-Subs.
* sub-instructions, D30V:                D30V-Subs.
* subexpressions:                        Arguments.
* subtitles for listings:                Sbttl.
* subtraction, permitted arguments:      Infix Ops.
* summary of options:                    Overview.
* support:                               HPPA-Dependent.
* supporting files, including:           Include.
* suppressing warnings:                  W.
* sval:                                  Z8000 Directives.
* symbol attributes:                     Symbol Attributes.
* symbol attributes, a.out:              a.out Symbols.
* symbol attributes, COFF:               COFF Symbols.
* symbol attributes, SOM:                SOM Symbols.
* symbol descriptor, COFF:               Desc.
* symbol names:                          Symbol Names.
* symbol names, $ in <1>:                SH-Chars.
* symbol names, $ in <2>:                D30V-Chars.
* symbol names, $ in <3>:                SH64-Chars.
* symbol names, $ in <4>:                H8/500-Chars.
* symbol names, $ in:                    D10V-Chars.
* symbol names, local:                   Symbol Names.
* symbol names, temporary:               Symbol Names.
* symbol storage class (COFF):           Scl.
* symbol type:                           Symbol Type.
* symbol type, COFF:                     Type.
* symbol type, ELF:                      Type.
* symbol value:                          Symbol Value.
* symbol value, setting:                 Set.
* symbol values, assigning:              Setting Symbols.
* symbol versioning:                     Symver.
* symbol, common:                        Comm.
* symbol, making visible to linker:      Global.
* symbolic debuggers, information for:   Stab.
* symbols:                               Symbols.
* Symbols in position-independent code, CRIS: CRIS-Pic.
* symbols with uppercase, VAX/VMS:       VAX-Opts.
* symbols, assigning values to:          Equ.
* symbols, local common:                 Lcomm.
* symver directive:                      Symver.
* syntax compatibility, i386:            i386-Syntax.
* syntax compatibility, x86-64:          i386-Syntax.
* syntax, D10V:                          D10V-Syntax.
* syntax, D30V:                          D30V-Syntax.
* syntax, M680x0:                        M68K-Syntax.
* syntax, M68HC11:                       M68HC11-Syntax.
* syntax, machine-independent:           Syntax.
* sysproc directive, i960:               Directives-i960.
* tab (\t):                              Strings.
* tag directive:                         Tag.
* tdaoff pseudo-op, V850:                V850 Opcodes.
* temporary symbol names:                Symbol Names.
* text and data sections, joining:       R.
* text directive:                        Text.
* text section:                          Ld Sections.
* tfloat directive, i386:                i386-Float.
* tfloat directive, x86-64:              i386-Float.
* thumb directive, ARM:                  ARM Directives.
* Thumb support:                         ARM-Dependent.
* thumb_func directive, ARM:             ARM Directives.
* thumb_set directive, ARM:              ARM Directives.
* time, total for assembly:              statistics.
* title directive:                       Title.
* tp register, V850:                     V850-Regs.
* trusted compiler:                      f.
* turning preprocessing on and off:      Preprocessing.
* type directive:                        Type.
* type of a symbol:                      Symbol Type.
* ualong directive, SH:                  SH Directives.
* uaword directive, SH:                  SH Directives.
* uleb128 directive:                     Uleb128.
* undefined section:                     Ld Sections.
* unsegm:                                Z8000 Directives.
* use directive, AMD 29K:                AMD29K Directives.
* V850 command line options:             V850 Options.
* V850 floating point (IEEE):            V850 Floating Point.
* V850 line comment character:           V850-Chars.
* V850 machine directives:               V850 Directives.
* V850 opcodes:                          V850 Opcodes.
* V850 options (none):                   V850 Options.
* V850 register names:                   V850-Regs.
* V850 support:                          V850-Dependent.
* val directive:                         Val.
* value attribute, COFF:                 Val.
* value of a symbol:                     Symbol Value.
* VAX bitfields not supported:           VAX-no.
* VAX branch improvement:                VAX-branch.
* VAX command-line options ignored:      VAX-Opts.
* VAX displacement sizing character:     VAX-operands.
* VAX floating point:                    VAX-float.
* VAX immediate character:               VAX-operands.
* VAX indirect character:                VAX-operands.
* VAX machine directives:                VAX-directives.
* VAX opcode mnemonics:                  VAX-opcodes.
* VAX operand notation:                  VAX-operands.
* VAX register names:                    VAX-operands.
* VAX support:                           Vax-Dependent.
* Vax-11 C compatibility:                VAX-Opts.
* VAX/VMS options:                       VAX-Opts.
* version of assembler:                  v.
* versions of symbols:                   Symver.
* Visibility <1>:                        Hidden.
* Visibility <2>:                        Protected.
* Visibility:                            Internal.
* VMS (VAX) options:                     VAX-Opts.
* warning for altered difference tables: K.
* warning messages:                      Errors.
* warnings, causing error:               W.
* warnings, M32R:                        M32R-Warnings.
* warnings, suppressing:                 W.
* warnings, switching on:                W.
* whitespace:                            Whitespace.
* whitespace, removed by preprocessor:   Preprocessing.
* wide floating point directives, VAX:   VAX-directives.
* Width of continuation lines of disassembly output: listing.
* Width of first line disassembly output: listing.
* Width of source line output:           listing.
* word directive:                        Word.
* word directive, ARC:                   ARC Directives.
* word directive, H8/300:                H8/300 Directives.
* word directive, H8/500:                H8/500 Directives.
* word directive, i386:                  i386-Float.
* word directive, M88K:                  M88K Directives.
* word directive, SPARC:                 Sparc-Directives.
* word directive, x86-64:                i386-Float.
* writing patterns in memory:            Fill.
* wval:                                  Z8000 Directives.
* x86-64 arch directive:                 i386-Arch.
* x86-64 att_syntax pseudo op:           i386-Syntax.
* x86-64 conversion instructions:        i386-Mnemonics.
* x86-64 floating point:                 i386-Float.
* x86-64 immediate operands:             i386-Syntax.
* x86-64 instruction naming:             i386-Mnemonics.
* x86-64 intel_syntax pseudo op:         i386-Syntax.
* x86-64 jump optimization:              i386-Jumps.
* x86-64 jump, call, return:             i386-Syntax.
* x86-64 jump/call operands:             i386-Syntax.
* x86-64 memory references:              i386-Memory.
* x86-64 options:                        i386-Options.
* x86-64 register operands:              i386-Syntax.
* x86-64 registers:                      i386-Regs.
* x86-64 sections:                       i386-Syntax.
* x86-64 size suffixes:                  i386-Syntax.
* x86-64 source, destination operands:   i386-Syntax.
* x86-64 support:                        i386-Dependent.
* x86-64 syntax compatibility:           i386-Syntax.
* xword directive, SPARC:                Sparc-Directives.
* Z800 addressing modes:                 Z8000-Addressing.
* Z8000 directives:                      Z8000 Directives.
* Z8000 line comment character:          Z8000-Chars.
* Z8000 line separator:                  Z8000-Chars.
* Z8000 opcode summary:                  Z8000 Opcodes.
* Z8000 options:                         Z8000 Options.
* Z8000 registers:                       Z8000-Regs.
* Z8000 support:                         Z8000-Dependent.
* zdaoff pseudo-op, V850:                V850 Opcodes.
* zero register, V850:                   V850-Regs.
* zero-terminated strings:               Asciz.


