; Copyright (C) 2005-2007 by Salvador E. Tropea (SET),
; see copyrigh file for details
;
; The following macros are designed for the Autoindent+Unindent mode.
; \n is new line.
; \b is backspace.
; \t is tab (not ASCII 9 but the smart tab)
; @0 is the position where the cursor is positioned after the insertion
; @1 is memorized in ^Q7 (or Alt7)
; @2 is memorized in ^Q8 (or Alt8)
; @3 is memorized in ^Q9 (or Alt9)
; @@ is a simple @
; @{Name} asks the user a value for "Name". Name becomes a variable.
; @{Name;Def} asks the user a value for "Name". Name becomes a variable. The
;             default value is "Def".
; @vN inserts the content of the "variable" number N. Variables are numbered
;     starting with 0.
; @{(sLisp)} executes the sLisp code.
; Don't put only @ at the end of the string :-).
;
;   The Mode keyword indicates the mode of the editor when the macro is
; triggered, each mode can be 0 or 1:
; Overwrite, Autoindent, Use Tabs, Persistent blocks, Inteligent C indent,
; Column cursor, Row cursor, Show match pair, idem on the fly, idem inmediatly,
; Transparent selection, Optimal fill, Wrap lines, Visible tabs, Don't move
; inside tabs, Tab key indents, Use indent size, Don't purge spaces and
; Backspace key unindents.
; For example: Mode: 0,1,0,1,0
; Indicates: No overwrite, autoindent, don't use real tabs, the blocks are
; persistent and don't be smart when indenting.
;   The Mode keyword can't be omitted.

Trigger: "ar"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Architecture
 "architecture @{Architecture} of @{Entity} is\n"
 "begin\n"
 "   @0;\n"
 "\bend architecture @v0; -- Entity: @v1"

Trigger: "bl"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Block
 "@{Label}:\n"
 "block\n"
 "begin\n"
 "   @0;\n"
 "\bend block @v0;"

Trigger: "co"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Component declaration
 "component @{Name} is\n"
 "   generic(@0\n"
    "       );\n"
    "\bport(@1\n"
    "     );\n"
 "\b\bend component @v0;"

Trigger: "ci"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Component instantiation
 "@{Label}: @{Component}\n"
 "   generic map(\n"
    "   @0 => @1,)\n"
    "\bport map(\n"
    "   @2 => @3,);\n"

Trigger: "wh"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Conditional signal assignment
 "@0 <= @1 when @2 else @3;"

Trigger: "#d"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Constant
 "constant @{Name} : @0:=@1;"

Trigger: "en"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Entity
 "entity @{Entity} is\n"
 "   generic(@0\n"
    "       );\n"
    "\bport(@1\n"
    "     );\n"
 "\b\bend entity @v0;"

Trigger: "ma"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Entity/Architecture
 "entity @{Entity} is\n"
 "   generic(@0\n"
    "       );\n"
    "\bport(@1\n"
    "     );\n"
 "\b\bend entity @v0;\n"
 "\n"
 "architecture @{Architecture} of @v0 is\n"
 "begin\n"
 "   ;\n"
 "\bend architecture @v1; -- Entity: @v0"

Trigger: "ex"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Exit
 "exit @{Label} when @0;"

Trigger: "fg"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: For generate
 "@{Label}:\n"
 "for @0 in @1 to @2 generate\n"
 "    @3;\n"
 "\bend generate @v0;"

Trigger: "f("
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: For loop
 "for @0 in @1 to @2 loop\n"
 "    @3;\n"
 "\bend loop;"

Trigger: "fu"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Function declaration
 "function @{Name}(@0) return @1 is\n"
 "begin\n"
 "   @2;\n"
 "\bend function @v0;"

Trigger: "li"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: IEEE standard libraries
 "library IEEE;\n"
 "use IEEE.std_logic_1164.all;\n"
 "use IEEE.numeric_std.all;\n\n"

Trigger: "ig"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: If generate
 "@{Label}:\n"
 "if @0 generate\n"
 "   @1;\n"
 "\bend generate @v0;"

Trigger: "I("
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: If, no else
 "if @0 then\n"
 "   @1;\n"
 "\bend if;"

Trigger: "i("
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: If plus else
 "if @0 then\n"
 "   @1;\n"
 "\belse\n"
 "   @2;\n"
 "\bend if;"

Trigger: "if"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: If/elsif/else/endif
 "if @0 then\n"
 "   @1;\n"
 "\belsif @2 then\n"
 "   @3;\n"
 "\belse\n"
 "   @4;\n"
 "\bend if;"

Trigger: "s("
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Case
 "case @0 is\n"
 "     when @1 =>\n"
      "     @2;\n"
      "\bwhen others =>\n"
      "     @3;\n"
 "\b\bend case;"

Trigger: "c:"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Case element (when)
 "when @0 =>\n"
 "     @2;"

Trigger: "#i"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Library/Use
 "library @{Library;IEEE};\n"
 "use @v0.@{Package;std_logic_1164}.all;"

Trigger: "ne"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Next
 "next @{Label} when @0;"

Trigger: "ot"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: (others => '')
 "(others => @{Value;'0'});"

Trigger: "pr"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Printf
 "printf(\"@0\");"

Trigger: "po"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Procedure declaration
 "procedure @{Name}(@0) is\n"
 "begin\n"
 "   @1;\n"
 "\bend procedure @v0;"

Trigger: "ps"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Process
 "@{Label}:\n"
 "process (@0)\n"
 "begin\n"
 "   @1;\n"
 "\bend process @v0;"

Trigger: "pc"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Process for clock
 "@{Label}:\n"
 "process (@{Clock;clk})\n"
 "begin\n"
 "   if rising_edge(@v1) then\n"
    "   @0;\n"
    "\bend if;\n"
 "\bend process @v0;"

Trigger: "p1"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Process w/clock+async rst
 "@{Label}:\n"
 "process (@{Clock;clk},@{Reset;rst})\n"
 "begin\n"
 "   if @v2='1' then\n"
    "   @0;\n"
    "\belsif rising_edge(@v1) then\n"
    "   @1;\n"
    "\bend if;\n"
 "\bend process @v0;"

Trigger: "p2"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Process w/clock+sync rst
 "@{Label}:\n"
 "process (@{Clock;clk},@{Reset;rst})\n"
 "begin\n"
 "   if rising_edge(@v1) then\n"
    "   if @v2='1' then\n"
       "   @0;\n"
       "\belse\n"
       "   @1;\n"
       "\bend if;\n"
    "\bend if;\n"
 "\bend process @v0;"

Trigger: "re"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Return
 "return @0;"

Trigger: "se"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Select signal (With)
 "with @{Expression} select @{Signal} <=\n"
 "     @{Value to assign} when @{Value for expression},\n"
      "@0when @1,\n"
      "@{Default value} when others;"

Trigger: "si"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Signal declaration
 "signal @{Name} : @0;"

Trigger: "sl"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Std_logic
 "std_logic"

Trigger: "sv"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Std_logic_vector
 "std_logic_vector(@0 downto @1)"

Trigger: "st"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Subtype
 "subtype @0 is @1 range @2 to @3;"

Trigger: "ty"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Type
 "type @0 is @1;"

Trigger: "un"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Unsigned
 "unsigned(@0 downto @1);"

Trigger: "#I"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Use
 "use @0.@1.all;"

Trigger: "va"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Variable declaration
 "variable @{Name} : @0;"

Trigger: "w("
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: While loop
 "while @0 loop\n"
 "   @1;\n"
 "\bend loop;"

Trigger: "pa"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Package
 "package @{Package} is\n"
 "   @0;\n"
 "\bend package @v0;"

Trigger: "pb"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Package body
 "package body @{Package} is\n"
 "   @0;\n"
 "\bend package body @v0;"

Trigger: "f1"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: D Flip Flop
 "@{Label;ffd_p}: -- D Flip Flop\n"
 "process (@{Clock;clk})\n"
 "begin\n"
 "   if rising_edge(@v1) then\n"
    "   @{Output;q} <= @{Input;d};\n"
    "\bend if;\n"
 "\bend process @v0;\n"

Trigger: "f2"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: D Flip Flop w/async reset
 "@{Label;ffd_p}: -- D Flip Flop w/async reset\n"
 "process (@{Clock;clk},@{Reset;rst})\n"
 "begin\n"
 "   if @v2='1' then\n"
    "   @{Output;q} <= '0';\n"
    "\belsif rising_edge(@v1) then\n"
    "   @v3 <= @{Input;d};\n"
    "\bend if;\n"
 "\bend process @v0;\n"

Trigger: "f3"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: D Flip Flop w/sync reset
 "@{Label;ffd_p}: -- D Flip Flop w/sync reset\n"
 "process (@{Clock;clk},@{Reset;rst})\n"
 "begin\n"
 "   if rising_edge(@v1) then\n"
    "   if @v2='1' then\n"
       "   @{Output;q} <= '0';\n"
       "\belse\n"
       "   @v3 <= @{Input;d};\n"
       "\bend if;\n"
    "\bend if;\n"
 "\bend process @v0;\n"

Trigger: "f4"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: D Flip Flop w/clock enable
 "@{Label;ffd_p}: -- D Flip Flop w/clock enable\n"
 "process (@{Clock;clk})\n"
 "begin\n"
 "   if rising_edge(@v1) then\n"
    "   if @{Enable;ena}='1' then\n"
       "   @{Output;q} <= @{Input;d};\n"
       "\bend if;\n"
    "\bend if;\n"
 "\bend process @v0;\n"

Trigger: "l1"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: D Latch
 "@{Label;latchd_p}: -- D Latch\n"
 "process (@{Gate;gate},@{Input;d})\n"
 "begin\n"
 "   if @v1='1' then\n"
    "   @{Output;q} <= @v2;\n"
    "\bend if;\n"
 "\bend process @v0;\n"

Trigger: "l2"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: D Latch w/reset
 "@{Label;latchd_p}: -- D Latch w/reset\n"
 "process (@{Gate;gate},@{Reset;rst},@{Input;d})\n"
 "begin\n"
 "   if @v2='1' then\n"
    "   @{Output;q} <= '0';\n"
    "\belsif @v1='1' then\n"
    "   @v4 <= @v3;\n"
    "\bend if;\n"
 "\bend process @v0;\n"

Trigger: "h1"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Hexa to 7-seg converter
 "-- Hexadecimal to 7-segment decoder\n"
 "-- @{Input;hex_val}:  in  std_logic_vector(3 downto 0);\n"
 "-- @{Output;seven_seg}:  out std_logic_vector(6 downto 0);\n"
 "--\n"
 "-- Bits used for each segment\n"
 "--      0\n"
 "--     ---\n"
 "--  5 |   | 1\n"
 "--     ---   <- 6\n"
 "--  4 |   | 2\n"
 "--     ---\n"
 "--      3\n"
 "-- Note: segments are active low.\n\n"
 "with @v0 select\n"
 "     @v1 <= \"1111001\" when \"0001\", -- 1\n"
      "       \"0100100\" when \"0010\", -- 2\n"
             "\"0110000\" when \"0011\", -- 3\n"
             "\"0011001\" when \"0100\", -- 4\n"
             "\"0010010\" when \"0101\", -- 5\n"
             "\"0000010\" when \"0110\", -- 6\n"
             "\"1111000\" when \"0111\", -- 7\n"
             "\"0000000\" when \"1000\", -- 8\n"
             "\"0010000\" when \"1001\", -- 9\n"
             "\"0001000\" when \"1010\", -- A\n"
             "\"0000011\" when \"1011\", -- b\n"
             "\"1000110\" when \"1100\", -- C\n"
             "\"0100001\" when \"1101\", -- d\n"
             "\"0000110\" when \"1110\", -- E\n"
             "\"0001110\" when \"1111\", -- F\n"
             "\"1000000\" when others; -- 0\n\n\b\b"

Trigger: "m1"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Multiplexer (logic version)
 "-- Multiplexer (logic version)\n"
 "-- @{Selection;sel}: in  std_logic_vector(@0 downto 0);\n"
 "-- @{Inputs;ins}: in  std_logic_vector(@1 downto 0);\n"
 "-- @{Output;ou}: out std_logic;\n\n"
 "@{Label;mux_logic_p}:\n"
 "process (@v0,@v1)\n"
 "   variable isel : integer;\n"
 "\bbegin\n"
 "   isel:=to_integer(unsigned(@v0));\n"
    "for i in ins'range loop\n"
    "    if i=isel then\n"
        "   @v2 <= @v1(isel);\n"
        "\bend if;\n"
    "\bend loop;\n"
 "\bend process @v3;\n"

Trigger: "m2"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Multiplexer (three state version)
 "-- Multiplexer (three state version)\n"
 "-- @{Selection;sel}: in  std_logic_vector(@0 downto 0);\n"
 "-- @{Inputs;ins}: in  std_logic_vector(@1 downto 0);\n"
 "-- @{Output;ou}: out std_logic;\n\n"
 "@{Label;mux_3s_p}:\n"
 "for i in @v1'range generate\n"
 "    @v2 <= @v1(i) when to_integer(unsigned(@v0))=i else 'Z';\n"
 "\bend generate @v0;"

Trigger: "s1"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Serial to Serial Shift Register
 "-- Serial-in and serial-out shift register\n"
 "-- @{Clock;clk}: in  std_logic;\n"
 "-- @{Input;sin}: in  std_logic;\n"
 "-- @{Output;sout}: out std_logic;\n"
 "-- signal @{Register;reg}: std_logic_vector(@{Bits-1;7} downto 0);\n\n"
 "@{Label;s2s_shift_p}:\n"
 "process (@v0)\n"
 "begin\n"
 "   if rising_edge(@v0) then\n"
    "   @v3 <= @v3(@v3'left-1 downto 0) & @v1;\n"
    "\bend if;\n"
    "@v2 <= @v3(@v3'left);\n"
 "\bend process @v5;"

Trigger: "s2"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Serial to Parallel Shift Register
 "-- Serial-in and parallel-out shift register\n"
 "-- @{Clock;clk}: in  std_logic;\n"
 "-- @{Input;sin}: in  std_logic;\n"
 "-- @{Output;pout}: out std_logic_vector(@{Bits-1;7} downto 0);\n"
 "-- signal @{Register;reg}: std_logic_vector(@v3 downto 0);\n\n"
 "@{Label;s2p_shift_p}:\n"
 "process (@v0)\n"
 "begin\n"
 "   if rising_edge(@v0) then\n"
    "   @v4 <= @v4(@v4'left-1 downto 0) & @v1;\n"
    "\bend if;\n"
    "@v2 <= @v4;\n"
 "\bend process @v5;"

Trigger: "s3"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Loadable Shift Register
 "-- Loadable serial-in and serial-out shift register\n"
 "-- @{Clock;clk}: in  std_logic;\n"
 "-- @{Input;sin}: in  std_logic;\n"
 "-- @{Load;load}: in  std_logic;\n"
 "-- @{Load Data;pin}: in  std_logic_vector(@{Bits-1;7} downto 0);\n"
 "-- @{Output;sout}: out std_logic;\n"
 "-- signal @{Register;reg}: std_logic_vector(@v4 downto 0);\n\n"
 "@{Label;s2s_wLoad_shift_p}:\n"
 "process (@v0)\n"
 "begin\n"
 "   if rising_edge(@v0) then\n"
    "   if @v2='1' then\n"
       "   @v6 <= @v3;\n"
       "\belse\n"
       "   @v6 <= @v6(@v6'left-1 downto 0) & @v1;\n"
       "\bend if;\n"
    "\bend if;\n"
    "@v5 <= @v6(@v6'left);\n"
 "\bend process @v7;"

Trigger: "c1"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: Counter w/load/dir/ena/reset
 "-- Synchronous counter with count enable, async reset and sync load\n"
; 0
 "-- @{Clock;clk}: in  std_logic;\n"
; 1
 "-- @{Reset;rst}: in  std_logic;\n"
; 2
 "-- @{Enable;ena}: in  std_logic;\n"
; 3
 "-- @{Load;load}: in  std_logic;\n"
; 4
 "-- @{Direction;dir}: in  std_logic;\n"
; 5-6
 "-- @{Data in;din}: in  std_logic_vector(@{Bits-1;7} downto 0);\n"
; 7
 "-- @{Output;cnt}: out std_logic_vector(@v6 downto 0);\n\n"
; 8
 "@{Label;counter_p}:\n"
 "process (@v0,@v1)\n"
 "   variable count : unsigned(@v6 downto 0);\n"
 "\bbegin\n"
 "   if @v1='1' then -- w/async reset\n"
    "   count <= (others => '0');\n"
    "\belsif rising_edge(@v0) then -- synchronous\n"
    "   if @v2='1' then -- w/enable\n"
       "   if @v3='1' then -- w/sync load\n"
          "   count <= @v5;\n"
          "\belse\n"
          "   if @v4='1' then -- w/direction\n"
             "   count:=count+1;\n"
             "\belse\n"
             "   count:=count-1;\n"
             "\bend if;\n"
          "\bend if;\n"
       "\bend if;\n"
    "\bend if;\n"
    "@v7 <= count;\n"
 "\bend process @v8;"

Trigger: "r1"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: RAM Single Port Distributed
 "library IEEE;\n"
 "use IEEE.std_logic_1164.all;\n"
 "use IEEE.numeric_std.all;\n\n"
 "entity @{Entity;SinglePortDistRAM} is\n"
 "   port(clk : in  std_logic;\n"
    "     we  : in  std_logic;\n"
         "addr: in  std_logic_vector(@{Bits addr-1;9} downto 0);\n"
         "di  : in  std_logic_vector(@{Bits data-1;7} downto 0);\n"
         "do  : out std_logic_vector(@v2 downto 0));\n"
 "\b\bend entity @v0;\n\n"
 "architecture Xilinx of @v0 is\n"
 "    type   ram_type is array(@{Size-1;1023} downto 0) of std_logic_vector (@v2 downto 0);\n"
     "signal ram : ram_type;\n"
 "\bbegin\n"
 "   the_ram:\n"
    "process (clk)\n"
    "begin\n"
    "   if rising_edge(clk) then\n"
       "   if we='1' then\n"
          "   ram(to_integer(unsigned(addr))) <= di;\n"
          "\bend if;\n"
       "\bend if;\n"
    "\bend process the_ram;\n\n"
    "do <= ram(to_integer(unsigned(addr)));\n"
 "\bend architecture Xilinx; -- Entity: @v0\n"

Trigger: "r2"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: RAM Dual Port Distributed
 "library IEEE;\n"
 "use IEEE.std_logic_1164.all;\n"
 "use IEEE.numeric_std.all;\n\n"
 "entity @{Entity;DualPortDistRAM} is\n"
 "   port(clk : in  std_logic;\n"
    "     we  : in  std_logic;\n"
         "add1: in  std_logic_vector(@{Bits addr-1;9} downto 0);\n"
         "add2: in  std_logic_vector(@v1 downto 0);\n"
         "di  : in  std_logic_vector(@{Bits data-1;7} downto 0);\n"
         "do1 : out std_logic_vector(@v2 downto 0);\n"
         "do2 : out std_logic_vector(@v2 downto 0));\n"
 "\b\bend entity @v0;\n\n"
 "architecture Xilinx of @v0 is\n"
 "    type   ram_type is array(@{Size-1;1023} downto 0) of std_logic_vector (@v2 downto 0);\n"
     "signal ram : ram_type;\n"
 "\bbegin\n"
 "   the_ram:\n"
    "process (clk)\n"
    "begin\n"
    "   if rising_edge(clk) then\n"
       "   if we='1' then\n"
          "   ram(to_integer(unsigned(add1))) <= di;\n"
          "\bend if;\n"
       "\bend if;\n"
    "\bend process the_ram;\n\n"
    "do1 <= ram(to_integer(unsigned(add1)));\n"
    "do2 <= ram(to_integer(unsigned(add2)));\n"
 "\bend architecture Xilinx; -- Entity: @v0\n"

Trigger: "b1"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: BRAM Single Port
 "library IEEE;\n"
 "use IEEE.std_logic_1164.all;\n"
 "use IEEE.numeric_std.all;\n\n"
 "entity @{Entity;SinglePortBRAM} is\n"
 "   port(clk : in  std_logic;\n"
    "     we  : in  std_logic;\n"
         "addr: in  std_logic_vector(@{Bits addr-1;9} downto 0);\n"
         "di  : in  std_logic_vector(@{Bits data-1;7} downto 0);\n"
         "do  : out std_logic_vector(@v2 downto 0));\n"
 "\b\bend entity @v0;\n\n"
 "architecture Xilinx of @v0 is\n"
 "    type   ram_type is array(@{Size-1;1023} downto 0) of std_logic_vector (@v2 downto 0);\n"
     "signal ram   : ram_type;\n"
     "signal read_a: std_logic_vector(@v1 downto 0);\n"
 "\bbegin\n"
 "   the_ram:\n"
    "process (clk)\n"
    "begin\n"
    "   if rising_edge(clk) then\n"
       "   if we='1' then\n"
          "   ram(to_integer(unsigned(addr))) <= di;\n"
          "\bend if;\n"
          "read_a <= addr;\n"
       "\bend if;\n"
    "\bend process the_ram;\n\n"
    "do <= ram(to_integer(unsigned(read_a)));\n"
 "\bend architecture Xilinx; -- Entity: @v0\n"

Trigger: "b2"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1
Name: BRAM Dual Port
 "library IEEE;\n"
 "use IEEE.std_logic_1164.all;\n"
 "use IEEE.numeric_std.all;\n\n"
 "entity @{Entity;DualPortBRAM} is\n"
 "   port(clk : in  std_logic;\n"
    "     we  : in  std_logic;\n"
         "add1: in  std_logic_vector(@{Bits addr-1;9} downto 0);\n"
         "add2: in  std_logic_vector(@v1 downto 0);\n"
         "di  : in  std_logic_vector(@{Bits data-1;7} downto 0);\n"
         "do1 : out std_logic_vector(@v2 downto 0);\n"
         "do2 : out std_logic_vector(@v2 downto 0));\n"
 "\b\bend entity @v0;\n\n"
 "architecture Xilinx of @v0 is\n"
 "    type   ram_type is array(@{Size-1;1023} downto 0) of std_logic_vector (@v2 downto 0);\n"
     "signal ram    : ram_type;\n"
     "signal read_a1: std_logic_vector(@v1 downto 0);\n"
     "signal read_a2: std_logic_vector(@v1 downto 0);\n"
 "\bbegin\n"
 "   the_ram:\n"
    "process (clk)\n"
    "begin\n"
    "   if rising_edge(clk) then\n"
       "   if we='1' then\n"
          "   ram(to_integer(unsigned(add1))) <= di;\n"
          "\bend if;\n"
          "read_a1 <= add1;\n"
          "read_a2 <= add2;\n"
       "\bend if;\n"
    "\bend process the_ram;\n\n"
    "do1 <= ram(to_integer(unsigned(read_a1)));\n"
    "do2 <= ram(to_integer(unsigned(read_a2)));\n"
 "\bend architecture Xilinx; -- Entity: @v0\n"

Trigger: "/i"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0,1,1
Name: File header (long)
 "------------------------------------------------------------------------------\n"
 "----                                                                      ----\n"
 "----  @{Title}\t----\n"
 "----                                                                      ----\n"
 "----  @{Downloaded from;Internal file, can't be downloaded.}\t----\n"
 "----                                                                      ----\n"
 "----  Description:                                                        ----\n"
 "----  @0                                                                    ----\n"
 "----                                                                      ----\n"
 "----  To Do:                                                              ----\n"
 "----  -                                                                   ----\n"
 "----                                                                      ----\n"
 "----  Author:                                                             ----\n"
 "----    - @{Author name}, @{e-mail}\t----\n"
 "----                                                                      ----\n"
 "------------------------------------------------------------------------------\n"
 "----                                                                      ----\n"
 "---- Copyright (c) @{"
; sLisp code to get the year using the date command. Side effect: saves the file to disk
 "(eval"
  "(setv 'year' (RunProgramRedir 'date +%Y'))"
  "(InsertText (left year (- (length year) 1)))"
 ")"
 "} @v2 <@v3>\t----\n"
 "----                                                                      ----\n"
 "---- @{License;For internal use, all rights reserved.}\t----\n"
 "----                                                                      ----\n"
 "------------------------------------------------------------------------------\n"
 "----\n"
 "---- Design unit:      @{Design unit;Entity(architecture) (Entity and architecture)}\n"
 "---- File name:        @{"
; sLisp code to get the filename and extension
 "(InsertText"
  "(+"
   "(WhichEditor edfWENameNoExt)"
   "(WhichEditor edfWEExtension)"
  ")"
 ")}\n"
 "---- Note:             None\n"
 "---- Limitations:      None known\n"
 "---- Errors:           None known\n"
 "---- Library:          @{Library;None}\n"
 "---- Dependencies:     IEEE.std_logic_1164\n"
 "----                   IEEE.numeric_std\n"
 "---- Target FPGA:      @{FPGA;Spartan II (XC2S100-5-PQ208)}\n"
 "---- Language:         VHDL\n"
 "---- Wishbone:         @{Wishbone;MASTER (rev B.3)}\n"
 "---- Synthesis tools:  @{Synthesis tools;Xilinx Release 6.2.03i - xst G.31a}\n"
 "---- Simulation tools: @{Simulation tools;GHDL [Sokcho edition] (0.1x)}\n"
 "---- Text editor:      SETEdit 0.5.x\n"
 "----\n"
; sLisp code to make the comment look like a "box" (16 lines)
 "@{(eval"
    "(repeat 17 (SendCommands cmcLineUp))"
    "(SendCommands cmcLineEnd)"
    "(repeat 16"
     "(SendCommands cmcCharLeft cmcCharLeft cmcCharLeft cmcCharLeft cmcLineDown)"
     "(InsertText '----')"
    ")"
    "(SendCommands cmcLineStart cmcLineDown)"
   ")}"
 "------------------------------------------------------------------------------\n"
 "--\n"
 "-- CVS Revision History\n"
 "--\n"
; We need to fool CVS ;-)
 "-- $"
 "Log$\n"
 "--\n"
 "--\n"

Trigger: "ri"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0,1,1
Name: rising_edge
 "rising_edge(@{Signal})"

Trigger: "fa"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0,1,1
Name: falling_edge
 "falling_edge(@{Signal})"

Trigger: "/d"
Mode: 0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0,1,1
Name: SDG Comment short
"---[txh]--------------------------------------------------------------------\n"
"--\n"
"--  Description:\n"
"--  @0\n"
"--\n"
"-------------------------------------------------------------------[/txh]---\n"

