Vst2Blif(1)

NAME
Vst2Blif - A filter that converts a structural vhdl source into a blif file.

SYNOPSIS
vst2blif [-h] [-v] [-u] [-s name] [-d name] [-c name] LibraryName [inputfile [outputfile]]

OPTIONS

Vst2Blif accepts the options described below:

-h  A brief summary of the allowed options are printed to standard error.

-v  All the warnings will be sent to standard output. See the Warning paragraph.

-u  Converts all actual terminals to uppercase.

-s name
    Uses "name" as the terminal for VSS, and eliminates all of the formals with this name. In fact the VHDL description used by Alliance includes the power lines, but SIS does not need them . So you may skip them by using this option for the VSS terminal and the next one for VDD. The default value is VSS.

-d name
    Uses "name" as the terminal for VDD. The default is VDD.

-c name
    Adds .clock "name" at the output file.

Disables the VSS and VDD checking.

Sets the initial value for latches, the default is 3 (=UNDEFINED)

LibraryName
    Is the full-path name of the library (in GENLIB format) to use for the conversion.

Input-File
    Is the name of the input file. If this name and the name of the output file are missing, stdin will be used as the input file.

Output-File
    Indicates the name of the output file. If it is missing, stdout will be used.

DESCRIPTION
The vst2blif program converts a structural vhdl file into a blif. The vhdl set supported is the same of the ALLIANCE CAD system (CAO-VLSI team at MASI laboratory, University P. et M. Curie 4, place Jussieu ; 75252 PARIS Cedex 05 ; FRANCE ; E-mail: cao-vlsi@masi.ibp.fr ). The syntax is a subset of the standard VHDL. The following examples will show the allowed keyword and how to use them:

ENTITY entity_name IS
GENERIC ( .. );
-- this will be ignored
PORT ( .. );
-- only BIT and BIT_VECTORS type of signals
END entity_name;
ARCHITECTURE type OF entity_name IS
-- multiple entities are allowed, but as they are declared
-- they must be followed by their architecture declarations.
SIGNAL ...
-- parsed but ignored
COMPONENT name
PORT( .. );
END COMPONENT;
-- No checks are carried out here. These strings are
-- just parsed.
-- SIGNAL clause and COMPONENT CLAUSE may be mixed
BEGIN
  name : ComponentName (
  	formal_terminal => actual_terminal;
	-- No vectors are allowed, only single elements of vectors
	.
	.
	);
-- and so on..
END type	;

EXAMPLE
Here is a simple half adder to show how the program works:
entity half_adder is
port (
  a,b     : in bit;  -- inputs
  sum     : out bit;
  carry   : out bit;
  clk     : in  bit; -- clock to latch the final result
  vdd,vss : in bit   -- power lines
  );
end half_adder;
architecture structural of halfadder is
component inv1x
port(
  a       : in bit;
  o       : out bit;
  vss,vdd : in bit
  );
end component;
component xor
port(
  a,b     : in bit;
  o       : out bit;
  vss,vdd : in bit
  );
end component;
component nand2
port(
  a,b     : in bit;
  o       : out bit;
  vss,vdd : in bit
  );
end component;
component dlatch
port(
  clk,d   : in bit;
  q       : out bit;
  vss,vdd : in bit
  );
end component;

signal carrytmp, sumtmp, carry_ : bit;
-- Note that the program will work perfectly even
-- without this declaration: SIS does not need the
-- declaration of the internal signals.
begin
 -- CARRY = a*b
 inst1 : nand2
 port map ( a => a, b => b, o  => carry_, vss => vss, vdd => vdd );
 inst2 : inv1x
 port map ( a => carry_, o => carrytmp, vss => vss, vdd => vdd);
 -- SUM = A xor B
 inst9 : xor
 port map ( a => a, b => b, o => sumtmp, vss => vss, vdd => vdd );
 -- let's save the result  in a latch
 instA : dlatch
 port map ( d => sumtmp, q => sum, clock => clk,
            vss => vss, vdd => vdd );
 instB : dlatch
 port map ( d => carrytmp, q => carry, clock => clk,
            vss => vss, vdd => vdd );
end structural;

This file will be converted using a command like this cat half.vst | vst2blif -c clk -v full_lib2.genlib > half.blif or, the equivalent one : vst2blif -c clk -v full_lib2.genlib half.vst half.blif Then the resul file will be:

 # File created by vst2blif ver 1.0
 .model half_adder
 .inputs a b
 .outputs sum carry
 .clock clk
 .gate nand2 a=a b=b O=carry_
 .gate inv1x a=carry_ O=carrytmp
 .gate xor a=a b=b O=sumtmp
 .mlatch dlatch D=sumtmp Q=sum clk 3
 .mlatch dlatch D=carrytmp Q=carry clk 3
 .end

The library used is the lib2.genlib and the lib2_latch.genlib merged toghether (into the fil efull_lib2.genlib). In fact the program takes as input only one library-file.

WARNINGS
As you may see the VHDL source has a lot of words (keywords) that this program can skip. Just consider the clause

COMPONENT name PORT ( formal1 : type; ... formal : type );

and consider the part with the PORT declaration. The tokenizer gives 2 tokens to the program : PORT and '(' , the first is necessary, but not the '('. Since we know that we are looking at a PORT CLAUSE,
 we expect a list of definitions of formal terminals. If the '(' is missing you will get a warning (it is a VHDL syntax error ) but this will not create any problem to the filter. This situation is true in other cases where there are more 'tokens' than the ones that will be stricly necessary. The program prints these warnings to the stderr if the option -v is given.

SEE ALSO
"The VHDL CookBook" By Peter J.Ashenden
                    chapter 3: "VHDL Describes Structure"

BUGS
Please reports any bugs to blaurea1@deis06.cineca.it