 
   July 1, 1994                                                        SIS(1)
 
   c_check -[nd] -[SH]#.#
 
     Verifies that the given circuit satisfies the constraints for correct
     clocking. By default the circuit is assumed to be mapped to a library.
     Use the -n option to use the _u_n_i_t-_f_a_n_o_u_t delay model.
 
     The user can give global set-up (and hold) times for all memory elements
     using the -S (-H) option. By default it computes the set-up and hold
     times from the library. _I_f _t_h_e _o_p_t_i_m_a_l _c_l_o_c_k_i_n_g _s_c_h_e_m_e _w_a_s _f_o_u_n_d _u_s_i_n_g
     _t_h_e _c__o_p_t _c_o_m_m_a_n_d make sure you use the same delay model!
 
     The -d value selects the debug level. The range is 1-5.
 
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