 
   July 1, 1994                                                        SIS(1)
 
   retime [-nfim] [-c #.#] [-t #.#] [-d #.#] [-a #.#] [-v #]
 
     Applies the retiming transformation on the circuit in an effort to
     reduce the cycle time. The retiming operation is supported only for sin-
     gle phase, edge-triggered designs. Both mapped and unmapped networks can
     be retimed.  The algorithm attempts to maintain the initial state infor-
     mation.
 
     The algorithm expects to work on mapped networks so that accurate delays
     on the gates can be used.  However, an unmapped network can be retimed
     by using the -n option.  In that case the delay through each node is
     computed according to the _u_n_i_t-_f_a_n_o_u_t delay model.  _T_h_e _u_s_e_r _s_h_o_u_l_d _b_e
     _a_w_a_r_e _o_f _t_h_e _f_a_c_t _t_h_a_t _w_h_e_n _r_e_t_i_m_i_n_g _c_i_r_c_u_i_t_s _c_o_n_t_a_i_n_i_n_g _c_o_m_p_l_e_x _r_e_g_i_s_-
     _t_e_r_s (_J_K, _D-_f_l_i_p _f_l_o_p_s _w_i_t_h _e_n_a_b_l_e_s/_p_r_e_s_e_t_s), _t_h_e _c_o_m_p_l_e_x _r_e_g_i_s_t_e_r_s _m_a_y
     _h_a_v_e _t_o _b_e _d_e_c_o_m_p_o_s_e_d _i_n_t_o _s_i_m_p_l_e_r _g_a_t_e_s.
 
     By default the algorithm uses a relaxation based approach which is very
     fast. An alternate formulation uses a mathematical programming formula-
     tion and can be selected using the -f option.  After profiling on a
     number of circuits only one will be retained.
 
     The -m option can be used to minimize the number of registers under
     cycle time constraints. If the cycle time is not specified using the -c
     option then this command will try to minimize the cycle time. Thus to
     obtain the absolute minimum number of registers for a circuit the user
     should specify a very loose cycle time constraint (very large value for
     the -c option).
 
     The retiming algorithm will try to compute the new initial states of the
     latches.  In case no feasible initial state exists the retiming is
     aborted and the network is not modified. To suppress the initialization
     routine use the -i option. In that case the initial values for all the
     latches after retiming is set to value of 2 (DONT_CARE).
 
     The desired clock period can be specified with the -c value option. When
     this option is not used the algorithm first checks to see if there is a
     cycle_time specification with the current network (the value depends on
     the current setting of the clock_flag in the network) and tries to meet
     this. If no cycle_time is specified with the design the retiming opera-
     tion tries to minimize the cycle time. For this it uses a binary search
     for testing feasible clock values. The tolerance of the binary search
     can be specified with the -t value option (the default is 0.1).
 
     Latches in the network can be assigned a propogation delay and an area.
     These are helpful in the realistic modelling of the circuit delay and
     area. Use the -d value option to specify the delay through a latch (to
     approximate the setup and propogation delay of the latch) and the -a
     value option to specify the area of a latch. In case of mapped networks,
     these values are automatically determined from the library of gates.
 
     The -v value selects the verbosity level. The range is 1-100 (100 will
     literally swamp you with a lot of unneeded data). Use the value 1 to see
     the progress of the algorithm.
 
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