# Tools Overview

# ASIMUT: VHDL simulator

- DESCRIPTION:
  ASIMUT is a VHDL simulator. It loads behavioral or structural descriptions written according to the Alliance VHDL subsets. ASIMUT may also be linked with C descriptions of behavioral components. It loads a stimuli file (PAT file format) and then run the simulation. The result is dumped in a new pattern file and it can be displayed using XPAT.
- STRENGTH
  Mixed simulation between C models and VHDL models.
- WEAKNESS
  ASIMUT is not a powerfull VHDL simulator compared to industrial one. It is used at LIP6 laboratory only for teaching purposes or small research projets. For example it doesn't take benefit of vectorized expressions, during compilation it splits them to an equivalent set of bits. During the simulation it interprets all boolean expressions, it is not effecient and it is very CPU time consuming compared to compiled and run methods. Finally, the VHDL subset it accepts is not standard and is very small. For example only boolean operators are supported, and only two VHDL types can be used (bit and bit vectors).
- DESIGN FLOW

# B2F: FSM abstractor

- DESCRIPTION:
  B2F is a Finite State Machine abstractor. It loads a RTL VHDL description (VBE file format). It then build the graph of an equivalent Finite State Machine, using a symbolic simulation algorithm. This tool does the inverse operation of the FSM synthesizer SYF
- STRENGTH
  None.
- WEAKNESS
  None.
- DESIGN FLOW

# BOOG: Binding and Optimizing On Gates

- DESCRIPTION:
  BOOG is used for the second step of the synthesis process. It loads a behavioural description (VBE) beforehand optimized with BOOM and builds an equivalent boolean network. It loads also a library of standard cells and in option a parameter file. For each boolean function of each node of the network, it tries to find in the given library, a cell or a set of cells that produce the same boolean function. This step is often called standard cell mapping. The result is a netlist of cells with an equivalent behavior.
- STRENGTH
  None.
- WEAKNESS
  BOOG is very archaic compared to industrial RTL synthesizer such as Synopsys. It's based on a pattern matching method which is not very efficient in particular for memorizing element mapping. The parameter file can only be used for global constraints, and for example it's not possible to impose a delay between to points in the resulting netlist.
- DESIGN FLOW

# BOOM: BOOlean Minimization

- DESCRIPTION:
  BOOM is used for the first step of the synthesis process. It loads a behavioural description (VBE), if possible a parameter file, and it builds an equivalent boolean network. From one hand it minimizes the boolean expression of each nodes of the network, and on the other hand it factorizes equivalent nodes. The result is an equivalent boolean network where the maximum depth is smaller and where boolean nodes have been factorized.
- STRENGTH
  BOOM gives good results (in term of literal's number) for small random logic descriptions.
- WEAKNESS
  BOOM is not powerfull compared to industrial RTL synthesizer such as Synopsys. It's based on a very original method (using BDD's) that often failed in particular for datapath optimization. As for BOOG the parameter file can only be used to specify global constraints. As for the VHDL simulator ASIMUT the VHDL subset it accepts is not standard and is very small.
- DESIGN FLOW

# COUGAR: Hierarchical netlist extractor

- DESCRIPTION:
  LYNX (called now COUGAR) is a hierarchical netlist extractor. It loads a symbolic or real physical view and given a technological file (RDS file format) it extracts a netlist.
- STRENGTH
  LYNX is a fast hierarchical netlist extractor. It is based on a simple but efficient algorithm with a CPU complexity between o(n) and o( n * sqrt(n)) (where n is the number of rectangles in the layout).
- WEAKNESS
  LYNX can not be compared to industrial netlist extractor. It uses a very poor pattern matching method for transistor recognition. It is no able to extract devices other than CMOS transistors, and it extracts parasitic capacitance and restistor with a very low precision.
- DESIGN FLOW

# DREAL: Design REAL layout

- DESCRIPTION:
  DREAL is the hierarchical real layout editor of Alliance.
- STRENGTH
  It is based on the same sources than GRAAL.
- WEAKNESS
  There are no integrated design rule checker and extractor.
- DESIGN FLOW
- SNAPSHOT:

# DRUC: Design REAL layout

- DESCRIPTION:
  DRUC is a hierarchical design rule checker. It loads a symbolic physical view and given a technological file (RDS file format) it verifies design rules.
- STRENGTH
  It has been sucessfully used for years at LIP6 laboratory.
- WEAKNESS
  DRUC works only on symbolic layout. The design rules have to specified in a pseudo french langage.
- DESIGN FLOW

# FLATBEH: Netlist abstractor

- DESCRIPTION:
  FLATBEH loads a hierarchical netlist and flats instances up to a given level (Leaf cells must have a RTL VHDL description). The result is an equivalent RTL VHDL description (VBE file format).
- STRENGTH
  None.
- WEAKNESS
  None.

# FLATLO: Flatten netlist

- DESCRIPTION:
  FLALO loads a hierarchical netlist and flats instances up to a given level. The result is a netlist description (VST/ AL file format).
- STRENGTH
  None.
- WEAKNESS
  None.

# FLATPH: Flatten hierarchical layout

- DESCRIPTION:
  FLAPH loads a hierarchical symbolic layout and flats instances up to a given level. The result is a new layout (AP file format).
- STRENGTH
  None.
- WEAKNESS
  None.

# FLATPH: Flatten hierarchical real layout

- DESCRIPTION:
  FLATRDS loads a hierarchical real layout and flats instances up to a given level. The result is a new real layout (CIF/GDS file format).
- STRENGTH
  None.
- WEAKNESS
  None.

# FMI: FSM minimization

- DESCRIPTION:
  FMI loads the graph of a Finite State Machine (FSM file format). In the given FSM, FMI finds all equivalent states and merges them all together. The result is a new FSM, that still equivalent, but with a reduced number of states. Finally it drives this new description using FSM file format.
- STRENGTH
  None.
- WEAKNESS
  None.
- DESIGN FLOW

# FSP: FSM equivalence checker

- DESCRIPTION:
  FSP is an FSM equivalence checker. It loads the graph of two FSMs and checks formally (using a FSM product based algorithm) if they have exactly the same behavior.
- STRENGTH
  None.
- WEAKNESS
  FSP does not use symbolic simulation technics and then it might consume a lot of memory and time for big FSMs.
- DESIGN FLOW

# GENLIB: Procedural Generation Language

- DESCRIPTION:
  GENLIB provides a C interface of a set of functions usefull to create a netlist of cells or a physical layout. For example given a cell library, a simple C function call is enough to create an instance of a cell. The result is a netlist (or a physical layout) built during the sequential execution of the C source code. GENLIB provides also a C interface for several macro-cells generators such as rom generator/register file generator etc ...
- STRENGTH
  Up to now GENLIB includes no less than 10 generators. The layout and the netlist of a complex data-path can be easily generated with only simple calls to predefined C functions.
- WEAKNESS
  None.
- DESIGN FLOW

# GENPAT: Procedural pattern file generator

- DESCRIPTION:
  GENPAT is used to write digital stimuli. It provides a C interface of a set of functions usefull to create stimuli. It loads a C file describing patterns and run the C compiler. Finally it generates a stimuli file. (PAT file format).
- STRENGTH
  None.
- WEAKNESS
  None.
- DESIGN FLOW

# GRAAL: Graphic layout editor

- DESCRIPTION:
  GRAAL is a hiearchical symbolic layout editor.
- STRENGTH
  GRAAL is one of the most famous tool of Alliance CAD system. It is easy to use and it displays layout fast. A design rule checker and a small extractor are integrated.
- WEAKNESS
  None.
- DESIGN FLOW
- SNAPSHOT:

# K2F: Kiss FSM translator

- DESCRIPTION:
  K2F is a FSM file format translator.
- STRENGTH
  None.
- WEAKNESS
  None.

# L2P: Layout to paper

- DESCRIPTION:
  L2P loads a physical layout (real or symbolic) and drives its drawing in a Postscript file.
- STRENGTH
  None.
- WEAKNESS
  For medium or huge design, the generated Postscript file takes a very long time to be printed. L2P uses very time comsuming Postscript functions.

# LOON: Local Optimization On Nets

- DESCRIPTION:
  LOON is used for the last step of the synthesis process. It loads a netlist of gates described in VHDL (VST). It loads also a library of standard cells and in option a parameter file. LOON computes the critical path and performs a gate repowering to decrease its delay and global capacitance. The result is an optimized netlist described in VHDL (VST).
- STRENGTH
  None.
- WEAKNESS
  LOON is very archaic compared to industrial RTL synthesizer such as Synopsys.
- DESIGN FLOW

# LVX: Gate netlist comparator

- DESCRIPTION:
  LVX is simple a netlist comparator.
- STRENGTH
  None.
- WEAKNESS
- DESIGN FLOW

# MOCHA: MOdel CHecker Ancestor

- DESCRIPTION:
  MOCHA loads the graph of a Finite State Machine description. This FSM is described in VHDL using predefined templates. Then it loads a list of CTL formulae (described in CTL file format) and check formally if the given FSM verify CTL properties. MOCHA can also be used on a behavioral description using the Alliance VHDL dataflow subset (VBE).
- STRENGTH/WEAKNESS
  This is a new tools and it has not been tested for now.
- DESIGN FLOW

# OCP: Placer for standard cell

- DESCRIPTION:
  OCP is a placement tool. It loads a netlist of standard cells. The designer can specifies eventually connectors placement by given a parameter file (IOC file format). If there are non standard cell blocks in the netlist, the designer has to give a placement for those blocks. OCP then uses a simulated annealing algorithm to find a placement of all the netlist's cells, that minimized the length of nets. The result is a physical symbolic layout file with physical connectors and placed cells (AP file format).
- STRENGTH
  OCP gives good results for small netlist (less than 500 gates).
- WEAKNESS
  OCP can not be compared to industrial place such as Cadence tools. There is a factor between 10 and 100 in term of CPU consumption for small or medium netlists (between 100 and 5000 gates).
- DESIGN FLOW

# NERO: Over-cell router

- DESCRIPTION:
  NERO is the over-cell router of Alliance. It loads a netlist and a physical placement file. The designer can give other parameters such as the number of metal layer he would like to use. The result is a physical symbolic layout view where each net of the netlist has been routed (AP file format).
- STRENGTH
  NERO gives good results for small netlist (less than 500 gates).
- WEAKNESS
  NERO can not be compared to industrial router such as Cadence tools. There is a factor between 10 and 100 in term of CPU consumption for small or medium netlists (between 100 and 5000 gates). Finally, for complex netlists with a high density of nets NERO may not converge.
- DESIGN FLOW

# PROOF: Equivalence Checker

- DESCRIPTION:
  PROOF is an equivalence checker. It loads two behavioural descriptions (VBE) and check their equivalence using formal technics.
- STRENGTH
  It is a very simple but very fast equivalence checker.
- WEAKNESS
  PROOF can only work if there is a bijection between the register's names of two description. This is NOT a real/full equivalence checker using complex symbolic simulation technics.
- DESIGN FLOW

# RDSX2Y: CIF/GDS translator

- DESCRIPTION:
  RDSX2Y is a real layout file format translator.
- STRENGTH
  RDSX2Y can be used to convert CIF or GDS files.
- WEAKNESS
  None.

# RING: Pad ring router

- DESCRIPTION:
  RING loads a netlist of pads interconnected with a "core" block. The designer can give a relative placement for those pads (RIN file format). After loading the physical view of the pads and the core, RING place and route them all together, with a special treatment for the power supply nets. The result is a physical symbolic layout (AP file format).
- STRENGTH
  None.
- WEAKNESS
  The clock supply net is treated like other nets, and RING is able to route only with two levels of metal.
- DESIGN FLOW

# S2R: Symbolic to Real layout

- DESCRIPTION:
  Given a technological file, S2R transforms a symbolic layout (lambda) to a real equivalent layout (micron).
- STRENGTH
  S2R is the keystone and the ultimate step of the symbolic and portable layout methodology. It has been used with success from years to transform symbolic portable layout to real layout for the foundry.
- WEAKNESS
  For now, a lot of problems have not been solved to use S2R with very deep sub-micron technology.
- DESIGN FLOW

# SCAPIN: Scan-path insertion tool

- DESCRIPTION:
  SCAPIN is an automatic scan path generator for gate level netlists. It loads a netlist (VST file format) and then inserts a scan path according to a parameter file. The result is a new netlist where a scan path has been inserted (VST file format).
- STRENGTH
  None.
- WEAKNESS
  It can insert only one scan-path in a netlist and it is not hierarchical.

# SYF: FSM Synthesizer

- DESCRIPTION:
  SYF loads the graph of a Finite State Machine. This FSM is described in VHDL using predefined templates. It encodes each states of the FSM and tries to minimize the resulting combinatorial logic. Finally it drives a new description using the Alliance VHDL dataflow subset (VBE file format).
- STRENGTH
  SYF is a good FSM synthesizer. It offers most common encoding algorithms and it verifies formally some very basic but usefull correctness properties.
- WEAKNESS
  The VHDL subset used to describe a FSM is very restricted
- DESIGN FLOW

# VASY: VHDL Analyzer for (RTL) SYnthesis

- DESCRIPTION:
  VASY can be seen as a VHDL translator. It loads VHDL behavioral or structural descriptions (written according to the Synopsys VHDL subset). It then drives one or more VHDL descriptions using the Alliance VHDL dataflow or structural subsets.
  Those Alliance VHDL subsets are small and very particular. They are called VBE (VHDL BEhavioral) and VST (VHDL STructural) file format.
- STRENGTH
  VASY allows to translate any RTL VHDL descriptions written under industrial environements to the small Alliance VHDL subset. It is often used to enter or to exit from the Alliance design flow. It is able also to translate any RTL VHDL descriptions into Verilog.
- WEAKNESS
  The VHDL compiler of VASY is very permissive and it doesn't verify the correctness of the input description (according to the VHDL standard reference manual). Another problem is that enumerate types are encoded and they disappear in the resulting VHDL description.
- DESIGN FLOW

# X2Y: Alliance file format translator

- DESCRIPTION:
  X2Y is a netlist or symbolic layout file format translator.
- STRENGTH
  X2Y can be used to translate Alliance internal file format to standard or industrial file format
- WEAKNESS
  None

# XFSM: Graphical FSM viewer

- DESCRIPTION:
  XFSM is a graphical FSM viewer. It loads a Finite State Machine description (FSM file format) and displays its graph on a graphical window.
- STRENGTH
  None.
- WEAKNESS
  XFSM can not be compared to industrial FSM or Graph editor.
- SNAPSHOT:

# XPAT: Graphical pattern viewer

- DESCRIPTION:
  XPAT is a graphical pattern viewer. It loads a pattern file (PAT file format) and displays waveforms on a graphical window.
- STRENGTH
  None.
- WEAKNESS
  XPAT can not be compared to industrial pattern viewer.
- DESIGN FLOW
- SNAPSHOT:

# XSCH: Graphical schematic viewer

- DESCRIPTION:
  XSCH is the graphical schematic viewer of Alliance. It loads a netlist (VST file format) and displays it on a graphical window.
- STRENGTH
  XSCH gives pretty results on small or medium standard cell netlist.
- WEAKNESS
  XSCH is not able to display vectors, all buses are split in set of nets. The consequence is that the drawing of big blocks netlist is very ugly.
- DESIGN FLOW
- SNAPSHOT:

# File format overview

# VHD: RTL VHDL file format

- This file format is used by VASY. It is very close to the Synopsys RTL VHDL subset:

                library IEEE;
                use IEEE.STD_LOGIC_1164.ALL;
                use IEEE.STD_LOGIC_arith.ALL;
                use IEEE.STD_LOGIC_unsigned.ALL;

                ENTITY ram IS
                  port ( A        : in std_logic_vector(5 downto 0);
                         CEB, WEB : in std_logic;
                         INN      : in  std_logic_vector(7 downto 0);
                         OUTT     : out std_logic_vector(7 downto 0)
                  );
                END ram;

                ARCHITECTURE dataflow_view OF ram IS

                  SUBTYPE TYPE_WORD IS std_logic_vector(7 downto 0);
                  TYPE TYPE_RAM IS ARRAY(63 DOWNTO 0) OF TYPE_WORD;
                  SIGNAL memory : TYPE_RAM;

                BEGIN

                  OUTT <= memory( CONV_INTEGER( A ) );

                  RAM_0 : PROCESS( CEB )
                  BEGIN
                   IF (CEB='1' AND CEB'EVENT )
                   THEN IF (WEB='0')
      	     THEN memory( CONV_INTEGER( A ) ) <= INN;
                        END IF;
                   END IF;

                  END PROCESS RAM_0;

                END dataflow_view;

# FSM: Finite State Machine file format

- This VHDL file format is used by tools such as SYF for FSM representation.

              ENTITY circuit is
              PORT
              ( ck    : in  BIT;
                jour  : in  BIT;
                reset : in  BIT;
                vdd   : in  BIT;
                vss   : in  BIT;
                i     : in  BIT_VECTOR(3 DOWNTO 0);
                porte : out BIT;
                alarm : out BIT
              );
              END circuit;
              ARCHITECTURE MOORE OF circuit is
                 TYPE ETAT_TYPE IS (E0, E1, E2, E3, E4, E5, EA);
                 SIGNAL EF, CS : ETAT_TYPE;
                 CONSTANT digit0 : BIT_VECTOR (3 DOWNTO 0) := B"1111"  ; -- O
                 ....
              --PRAGMA CURRENT_STATE CS
              --PRAGMA NEXT_STATE EF
              --PRAGMA CLOCK ck
              --PRAGMA FIRST_STATE E0

              BEGIN
              PROCESS ( CS, i)
              BEGIN
                IF ( reset = '1' )
                THEN
                  EF    <= E0; porte <= '0'; alarm <= '0'; ELSE
                CASE CS is
      	  WHEN E0 =>
                    porte <= '0'; alarm <= '0';
                    IF ( i = digit0 ) THEN
                      IF ( jour = '1' ) THEN EF <= E5;
                      ELSE EF <= EA;
                      END IF;
                    ELSE
                      IF ( i = digit1 ) THEN EF <= E1;
                      ELSE IF ( jour = '1' ) THEN EF <= E0;
                        ELSE EF <= EA;
                        END IF;
                      END IF;
                    END IF;

      	  WHEN E1 =>
                  ....
                END CASE;
                END IF;
              END PROCESS;

              PROCESS( ck )
              BEGIN
                  IF ( ck = '1' AND NOT ck'STABLE ) THEN CS <= EF;
                  END IF;
              END PROCESS;
              END MOORE;

# VBE: Alliance VHDL dataflow file format

- This file format is used by most of the Alliance tools for RTL behavioral descriptions. It is a very particular and non standard VHDL subset:

              ENTITY addaccu IS
              PORT(
                clr	: IN BIT;
                ld	: IN BIT;
                outs	: IN BIT_VECTOR(15 DOWNTO 0);
                clk	: IN BIT;
                result	: OUT BIT_VECTOR(15 DOWNTO 0);
                vdd	: IN BIT;
                vss	: IN BIT
              );
              END addaccu;

              ARCHITECTURE VBE OF addaccu IS

                SIGNAL rtlsum_0	: BIT_VECTOR(15 DOWNTO 0);
                SIGNAL rtlcarry_0	: BIT_VECTOR(15 DOWNTO 0);
                SIGNAL resultint	: REG_VECTOR(15 DOWNTO 0) REGISTER;
              BEGIN

                rtlcarry_0(0) < '0';
                rtlsum_0 < ((resultint XOR outs) XOR rtlcarry_0);
                rtlcarry_0(15 downto 1) < (((resultint(14 downto 0) AND outs(14 downto 0)) OR
                    (resultint(14 downto 0) AND rtlcarry_0(14 downto 0))) OR
                    (outs(14 downto 0) AND rtlcarry_0(14 downto 0)));
                result < resultint;

                LABEL1 : BLOCK  ((clk = '1') AND NOT(clk'STABLE) )
                BEGIN
                  resultint < GUARDED "0000000000000000" WHEN clr ELSE
                   rtlsum_0 WHEN (NOT(clr) AND ld) ELSE resultint;
                END BLOCK LABEL1;
              END VBE;

# VST: Alliance VHDL structural file format

- This file format is used by most of the Alliance tools for gate netlist descriptions (structural VHDL):

              ENTITY digi IS
                PORT (
                ck : in BIT ;
                jour : in BIT ;
                reset : in BIT ;
                vdd : in BIT ;
                vss : in BIT ;
                i : in BIT_VECTOR(3 DOWNTO 0) ;
                porte : out BIT ;
                alarm : out BIT
                );
              END digi;

              ARCHITECTURE VST OF digi IS
                COMPONENT nxr2_x1
                  port (
                  i0 : in BIT ;
                  i1 : in BIT ;
                  nq : out BIT ;
                  vdd : in BIT ;
                  vss : in BIT
                  );
                END COMPONENT;
      	  ....
                SIGNAL mbk_buf_not_aux1 : BIT;
      	  ....
              BEGIN
                not_aux12_ins : nxr2_x1
                  PORT MAP (
                  vss => vss,
                  vdd => vdd,
                  nq => not_aux12,
                  i1 => i(3),
      	    i0 => i(1));
      	    ....
              end VST;

# PAT: Alliance Pattern file format

- This file format is used by Alliance tools for pattern specification and digital simulation results:

              in       clk B;;
              in       rst B;;
              in       stb B;;
              in       a (7 downto 0) X;;
              in       b (7 downto 0) X;;
              out      result (15 downto 0) X;;
              out      done B;
              begin
                  ....
                  : 1 0 0 00 00 ?0006 ?0;
                  : 0 0 0 00 00 ?0006 ?0;
                  : 1 0 0 00 00 ?0006 ?1;
                  : 0 0 0 00 00 ?0006 ?1;
                  : 1 0 0 00 00 ?0006 ?1;
                  : 0 0 0 00 00 ?0006 ?1;
              end;

# AP: Alliance symbolic layout file format

- This file format is used by Alliance tools for the hierarchical symbolic layout representation (lambda stick diagram):

              V ALLIANCE : 6
              H digi,P, 1/10/2002,100
              A 0,0,28000,30000
              C 28000,29700,600,vdd,7,EAST,ALU1
              C 21000,0,200,alarm,0,SOUTH,ALU2
              C 2000,30000,200,ck,0,NORTH,ALU2
              ....
              S 0,25000,28000,25000,1200,vss,RIGHT,ALU1
              S 0,20000,28000,20000,1200,vdd,RIGHT,ALU1
              S 0,10000,28000,10000,1200,vdd,RIGHT,ALU1
              ....
              I 24000,0,a3_x2,a3_x2_4_ins,SYM_Y
              I 4000,0,na2_x1,na2_x1_2_ins,SYM_Y
              ....
              V 2000,29500,CONT_VIA2,*
              V 2000,30000,CONT_VIA2,*
              V 2500,14000,CONT_VIA2,*
              V 2500,19000,CONT_VIA2,*
              ...
              EOF

# AL: Alliance netlist file format

- This file format is used by Alliance tools to represent a hierarchical gate and/or transistor netlist with eventually RC networks:

              V ALLIANCE : 6
              H digi_e,L,01/10/2002
              C alarm,UNKNOWN,EXTERNAL,12
              C ck,UNKNOWN,EXTERNAL,40
              ...
              C vdd,UNKNOWN,EXTERNAL,1
              C vss,UNKNOWN,EXTERNAL,21
              I na2_x1,na2_x1_2_ins
              C i0,UNKNOWN,INTERNAL,4
              C i1,UNKNOWN,INTERNAL,6
              ...
              S 4,INTERNAL,not_aux14
              S 3,INTERNAL,circuit_cs_0
              S 2,INTERNAL,circuit_cs_2
              S 1,EXTERNAL,vdd
              EOF

# Main libraries overview

# MUT: MBK utilities

- This library is used by all Alliance tools and other libraries. It provides a lot of small utility functions like strings hashing, hash tables, memory allocation function etc ...

# MLO: MBK logical

- This library is used to describe a hierarchical netlist (of gates or transistors) and also R/C networks. It provides a data structure called lofig and several methods to create/search/destroy elements in this DB. It provides also parsers/drivers for several file format such as SPICE, VHDL, FNE or HNS (COMPASS file format), and AL (Alliance format).

# MPH: MBK physical

- This library is used to describe a hierarchical symbolic layout (in lambda). It provides a data structure called phfig and several methods to create/search/destroy elements in this DB. It provides also parsers/drivers for several file format such as CP (COMPASS file format) and AP (Alliance file format).

# RDS: Rectangle Data Structure

- This library is used to describe a hierarchical real layout (in micron). It provides a data structure called rdsfig and several methods to create/search/destroy elements in this DB. It provides also parsers/drivers for several file format such as GDS or CIF.

# BEH: Behavioral Figure

- This library is used to describe the RTL behaviour of a circuit. It provides a data structure called befig and several methods to create/search/destroy elements in this DB. It provides also a parser/driver (VHDL file format).

# FSM: Finite State Machine

- This library is used to describe the FSM. It provides a data structure called fsmfig and several methods to create/search/destroy elements in this DB. It provides also a parser/driver (VHDL and KISS2 file format).

# BDD: Binary Decision Diagram

- This library is used to describe BDD's. It provides a data structure called bddcircuit and several methods to manipulate BDDs efficiently.

# ABL: LISP Binary tree

- This library is used to describe boolean expression. It provides a data structure called ablexpr and several methods to manipulate boolean expression efficiently.

# PAT: PATtern

- This library is used to describe digital stimuli. It is used by digital simulation tools. It provides a parser/driver (PAT file format).