entity amd2901_ctl is
   port (
      ops_mx        : out     bit_vector(2 downto 0);
      opr_mx        : out     bit_vector(1 downto 0);
      alu_k         : out     bit_vector(4 downto 0);
      alu_cout      : in      bit;
      alu_over      : in      bit;
      ram_sh        : out     bit_vector(1 downto 0);
      out_mx        : out     bit;
      acc_wen       : out     bit;
      alu_f         : in      bit_vector(3 downto 0);
      alu_np        : in      bit_vector(3 downto 0);
      alu_ng        : in      bit_vector(3 downto 0);
      core_test     : in      bit;
      core_fonc     : in      bit;
      core_np       : out     bit;
      core_ng       : out     bit;
      core_over     : out     bit;
      core_zero     : out     bit;
      core_sh_right : out     bit;
      core_sh_left  : out     bit;
      i             : in      bit_vector(8 downto 0);
      noe           : in      bit;
      oe            : out     bit;
      a             : in      bit_vector(3 downto 0);
      b             : in      bit_vector(3 downto 0);
      deca          : out     bit_vector(15 downto 0);
      decb          : out     bit_vector(15 downto 0);
      decwb         : out     bit_vector(15 downto 0);
      vdd           : in      bit;
      vss           : in      bit
 );
end amd2901_ctl;

architecture structural of amd2901_ctl is
Component inv_x4
   port (
      i   : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component na4_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component inv_x2
   port (
      i   : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component a4_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component na3_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component no3_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component o2_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component a3_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component xr2_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component na2_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component a2_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component no2_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component noa22_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component inv_x1
   port (
      i   : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

signal na            : bit_vector( 3 downto 0);
signal nb            : bit_vector( 3 downto 0);
signal ni            : bit_vector( 6 downto 0);
signal ram_wri       : bit;
signal ram_nwri      : bit;
signal ram_nwen      : bit;
signal ram_adrb_9    : bit;
signal ram_adrb_8    : bit;
signal ram_adrb_7    : bit;
signal ram_adrb_6    : bit;
signal ram_adrb_5    : bit;
signal ram_adrb_4    : bit;
signal ram_adrb_3    : bit;
signal ram_adrb_2    : bit;
signal ram_adrb_15   : bit;
signal ram_adrb_14   : bit;
signal ram_adrb_13   : bit;
signal ram_adrb_12   : bit;
signal ram_adrb_11   : bit;
signal ram_adrb_10   : bit;
signal ram_adrb_1    : bit;
signal ram_adrb_0    : bit;
signal opr_mx1_1     : bit;
signal opr_mx1_0     : bit;
signal fonc_mode     : bit;
signal core_nfonc    : bit;
signal alu_zero_1    : bit;
signal alu_zero_0    : bit;
signal alu_p_1       : bit;
signal alu_p_0       : bit;
signal alu_k4_0      : bit;
signal alu_g_6       : bit;
signal alu_g_5       : bit;
signal alu_g_4       : bit;
signal alu_g_3       : bit;
signal alu_g_2       : bit;
signal alu_g_1       : bit;
signal alu_g_0       : bit;

begin

inv_a0 : inv_x4
   port map (
      i   => a(0),
      nq  => na(0),
      vdd => vdd,
      vss => vss
   );

inv_a1 : inv_x4
   port map (
      i   => a(1),
      nq  => na(1),
      vdd => vdd,
      vss => vss
   );

inv_a2 : inv_x4
   port map (
      i   => a(2),
      nq  => na(2),
      vdd => vdd,
      vss => vss
   );

inv_a3 : inv_x4
   port map (
      i   => a(3),
      nq  => na(3),
      vdd => vdd,
      vss => vss
   );

inv_b0 : inv_x4
   port map (
      i   => b(0),
      nq  => nb(0),
      vdd => vdd,
      vss => vss
   );

inv_b1 : inv_x4
   port map (
      i   => b(1),
      nq  => nb(1),
      vdd => vdd,
      vss => vss
   );

inv_b2 : inv_x4
   port map (
      i   => b(2),
      nq  => nb(2),
      vdd => vdd,
      vss => vss
   );

inv_b3 : inv_x4
   port map (
      i   => b(3),
      nq  => nb(3),
      vdd => vdd,
      vss => vss
   );

inv_wen : inv_x4
   port map (
      i   => ram_wri,
      nq  => ram_nwen,
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_0_0 : na4_x1
   port map (
      i0  => nb(3),
      i1  => nb(2),
      i2  => nb(1),
      i3  => nb(0),
      nq  => ram_adrb_0,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_0_1 : inv_x2
   port map (
      i   => ram_adrb_0,
      nq  => decb(0),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_0_0 : no2_x1
   port map (
      i0  => ram_adrb_0,
      i1  => ram_nwen,
      nq  => decwb(0),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_0_0 : a4_x2
   port map (
      i0  => na(3),
      i1  => na(2),
      i2  => na(1),
      i3  => na(0),
      q   => deca(0),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_1_0 : na4_x1
   port map (
      i0  => nb(3),
      i1  => nb(2),
      i2  => nb(1),
      i3  => b(0),
      nq  => ram_adrb_1,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_1_1 : inv_x2
   port map (
      i   => ram_adrb_1,
      nq  => decb(1),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_1_0 : no2_x1
   port map (
      i0  => ram_adrb_1,
      i1  => ram_nwen,
      nq  => decwb(1),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_1_0 : a4_x2
   port map (
      i0  => na(3),
      i1  => na(2),
      i2  => na(1),
      i3  => a(0),
      q   => deca(1),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_2_0 : na4_x1
   port map (
      i0  => nb(3),
      i1  => nb(2),
      i2  => b(1),
      i3  => nb(0),
      nq  => ram_adrb_2,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_2_1 : inv_x2
   port map (
      i   => ram_adrb_2,
      nq  => decb(2),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_2_0 : no2_x1
   port map (
      i0  => ram_adrb_2,
      i1  => ram_nwen,
      nq  => decwb(2),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_2_0 : a4_x2
   port map (
      i0  => na(3),
      i1  => na(2),
      i2  => a(1),
      i3  => na(0),
      q   => deca(2),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_3_0 : na4_x1
   port map (
      i0  => nb(3),
      i1  => nb(2),
      i2  => b(1),
      i3  => b(0),
      nq  => ram_adrb_3,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_3_1 : inv_x2
   port map (
      i   => ram_adrb_3,
      nq  => decb(3),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_3_0 : no2_x1
   port map (
      i0  => ram_adrb_3,
      i1  => ram_nwen,
      nq  => decwb(3),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_3_0 : a4_x2
   port map (
      i0  => na(3),
      i1  => na(2),
      i2  => a(1),
      i3  => a(0),
      q   => deca(3),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_4_0 : na4_x1
   port map (
      i0  => nb(3),
      i1  => b(2),
      i2  => nb(1),
      i3  => nb(0),
      nq  => ram_adrb_4,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_4_1 : inv_x2
   port map (
      i   => ram_adrb_4,
      nq  => decb(4),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_4_0 : no2_x1
   port map (
      i0  => ram_adrb_4,
      i1  => ram_nwen,
      nq  => decwb(4),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_4_0 : a4_x2
   port map (
      i0  => na(3),
      i1  => a(2),
      i2  => na(1),
      i3  => na(0),
      q   => deca(4),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_5_0 : na4_x1
   port map (
      i0  => nb(3),
      i1  => b(2),
      i2  => nb(1),
      i3  => b(0),
      nq  => ram_adrb_5,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_5_1 : inv_x2
   port map (
      i   => ram_adrb_5,
      nq  => decb(5),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_5_0 : no2_x1
   port map (
      i0  => ram_adrb_5,
      i1  => ram_nwen,
      nq  => decwb(5),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_5_0 : a4_x2
   port map (
      i0  => na(3),
      i1  => a(2),
      i2  => na(1),
      i3  => a(0),
      q   => deca(5),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_6_0 : na4_x1
   port map (
      i0  => nb(3),
      i1  => b(2),
      i2  => b(1),
      i3  => nb(0),
      nq  => ram_adrb_6,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_6_1 : inv_x2
   port map (
      i   => ram_adrb_6,
      nq  => decb(6),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_6_0 : no2_x1
   port map (
      i0  => ram_adrb_6,
      i1  => ram_nwen,
      nq  => decwb(6),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_6_0 : a4_x2
   port map (
      i0  => na(3),
      i1  => a(2),
      i2  => a(1),
      i3  => na(0),
      q   => deca(6),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_7_0 : na4_x1
   port map (
      i0  => nb(3),
      i1  => b(2),
      i2  => b(1),
      i3  => b(0),
      nq  => ram_adrb_7,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_7_1 : inv_x2
   port map (
      i   => ram_adrb_7,
      nq  => decb(7),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_7_0 : no2_x1
   port map (
      i0  => ram_adrb_7,
      i1  => ram_nwen,
      nq  => decwb(7),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_7_0 : a4_x2
   port map (
      i0  => na(3),
      i1  => a(2),
      i2  => a(1),
      i3  => a(0),
      q   => deca(7),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_8_0 : na4_x1
   port map (
      i0  => b(3),
      i1  => nb(2),
      i2  => nb(1),
      i3  => nb(0),
      nq  => ram_adrb_8,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_8_1 : inv_x2
   port map (
      i   => ram_adrb_8,
      nq  => decb(8),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_8_0 : no2_x1
   port map (
      i0  => ram_adrb_8,
      i1  => ram_nwen,
      nq  => decwb(8),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_8_0 : a4_x2
   port map (
      i0  => a(3),
      i1  => na(2),
      i2  => na(1),
      i3  => na(0),
      q   => deca(8),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_9_0 : na4_x1
   port map (
      i0  => b(3),
      i1  => nb(2),
      i2  => nb(1),
      i3  => b(0),
      nq  => ram_adrb_9,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_9_1 : inv_x2
   port map (
      i   => ram_adrb_9,
      nq  => decb(9),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_9_0 : no2_x1
   port map (
      i0  => ram_adrb_9,
      i1  => ram_nwen,
      nq  => decwb(9),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_9_0 : a4_x2
   port map (
      i0  => a(3),
      i1  => na(2),
      i2  => na(1),
      i3  => a(0),
      q   => deca(9),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_10_0 : na4_x1
   port map (
      i0  => b(3),
      i1  => nb(2),
      i2  => b(1),
      i3  => nb(0),
      nq  => ram_adrb_10,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_10_1 : inv_x2
   port map (
      i   => ram_adrb_10,
      nq  => decb(10),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_10_0 : no2_x1
   port map (
      i0  => ram_adrb_10,
      i1  => ram_nwen,
      nq  => decwb(10),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_10_0 : a4_x2
   port map (
      i0  => a(3),
      i1  => na(2),
      i2  => a(1),
      i3  => na(0),
      q   => deca(10),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_11_0 : na4_x1
   port map (
      i0  => b(3),
      i1  => nb(2),
      i2  => b(1),
      i3  => b(0),
      nq  => ram_adrb_11,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_11_1 : inv_x2
   port map (
      i   => ram_adrb_11,
      nq  => decb(11),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_11_0 : no2_x1
   port map (
      i0  => ram_adrb_11,
      i1  => ram_nwen,
      nq  => decwb(11),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_11_0 : a4_x2
   port map (
      i0  => a(3),
      i1  => na(2),
      i2  => a(1),
      i3  => a(0),
      q   => deca(11),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_12_0 : na4_x1
   port map (
      i0  => b(3),
      i1  => b(2),
      i2  => nb(1),
      i3  => nb(0),
      nq  => ram_adrb_12,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_12_1 : inv_x2
   port map (
      i   => ram_adrb_12,
      nq  => decb(12),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_12_0 : no2_x1
   port map (
      i0  => ram_adrb_12,
      i1  => ram_nwen,
      nq  => decwb(12),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_12_0 : a4_x2
   port map (
      i0  => a(3),
      i1  => a(2),
      i2  => na(1),
      i3  => na(0),
      q   => deca(12),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_13_0 : na4_x1
   port map (
      i0  => b(3),
      i1  => b(2),
      i2  => nb(1),
      i3  => b(0),
      nq  => ram_adrb_13,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_13_1 : inv_x2
   port map (
      i   => ram_adrb_13,
      nq  => decb(13),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_13_0 : no2_x1
   port map (
      i0  => ram_adrb_13,
      i1  => ram_nwen,
      nq  => decwb(13),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_13_0 : a4_x2
   port map (
      i0  => a(3),
      i1  => a(2),
      i2  => na(1),
      i3  => a(0),
      q   => deca(13),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_14_0 : na4_x1
   port map (
      i0  => b(3),
      i1  => b(2),
      i2  => b(1),
      i3  => nb(0),
      nq  => ram_adrb_14,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_14_1 : inv_x2
   port map (
      i   => ram_adrb_14,
      nq  => decb(14),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_14_0 : no2_x1
   port map (
      i0  => ram_adrb_14,
      i1  => ram_nwen,
      nq  => decwb(14),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_14_0 : a4_x2
   port map (
      i0  => a(3),
      i1  => a(2),
      i2  => a(1),
      i3  => na(0),
      q   => deca(14),
      vdd => vdd,
      vss => vss
   );

na4_ram_adrb_15_0 : na4_x1
   port map (
      i0  => b(3),
      i1  => b(2),
      i2  => b(1),
      i3  => b(0),
      nq  => ram_adrb_15,
      vdd => vdd,
      vss => vss
   );

n1_ram_adrb_15_1 : inv_x2
   port map (
      i   => ram_adrb_15,
      nq  => decb(15),
      vdd => vdd,
      vss => vss
   );

no2_ram_adri_15_0 : no2_x1
   port map (
      i0  => ram_adrb_15,
      i1  => ram_nwen,
      nq  => decwb(15),
      vdd => vdd,
      vss => vss
   );

a4_ram_adra_15_0 : a4_x2
   port map (
      i0  => a(3),
      i1  => a(2),
      i2  => a(1),
      i3  => a(0),
      q   => deca(15),
      vdd => vdd,
      vss => vss
   );

n1_i2 : inv_x1
   port map (
      i   => i(2),
      nq  => ni(2),
      vdd => vdd,
      vss => vss
   );

n1_i1 : inv_x1
   port map (
      i   => i(1),
      nq  => ni(1),
      vdd => vdd,
      vss => vss
   );

n1_i0 : inv_x1
   port map (
      i   => i(0),
      nq  => ni(0),
      vdd => vdd,
      vss => vss
   );

no2_ops_mx0 : no2_x1
   port map (
      i0  => i(2),
      i1  => ni(0),
      nq  => ops_mx(0),
      vdd => vdd,
      vss => vss
   );

no2_ops_mx1 : no2_x1
   port map (
      i0  => ni(2),
      i1  => i(1),
      nq  => ops_mx(1),
      vdd => vdd,
      vss => vss
   );

a3_ops_mx2 : a3_x2
   port map (
      i0  => i(2),
      i1  => i(1),
      i2  => i(0),
      q   => ops_mx(2),
      vdd => vdd,
      vss => vss
   );

o2_opr_mx0 : o2_x2
   port map (
      i0  => i(2),
      i1  => i(1),
      q   => opr_mx(0),
      vdd => vdd,
      vss => vss
   );

na2_opr_mx1_0 : na2_x1
   port map (
      i0  => ni(2),
      i1  => i(1),
      nq  => opr_mx1_0,
      vdd => vdd,
      vss => vss
   );

na3_opr_mx1_1 : na3_x1
   port map (
      i0  => i(2),
      i1  => ni(1),
      i2  => ni(0),
      nq  => opr_mx1_1,
      vdd => vdd,
      vss => vss
   );

na2_opr_mx1_2 : na2_x1
   port map (
      i0  => opr_mx1_0,
      i1  => opr_mx1_1,
      nq  => opr_mx(1),
      vdd => vdd,
      vss => vss
   );

n1_i3 : inv_x1
   port map (
      i   => i(7),
      nq  => ni(3),
      vdd => vdd,
      vss => vss
   );

no3_out_mx0 : no3_x1
   port map (
      i0  => i(8),
      i1  => ni(3),
      i2  => i(6),
      nq  => out_mx,
      vdd => vdd,
      vss => vss
   );

xr2_alu_k0 : xr2_x1
   port map (
      i0  => i(5),
      i1  => i(3),
      q   => alu_k(0),
      vdd => vdd,
      vss => vss
   );

xr2_alu_k1 : xr2_x1
   port map (
      i0  => i(5),
      i1  => i(4),
      q   => alu_k(1),
      vdd => vdd,
      vss => vss
   );

n1_i4 : inv_x1
   port map (
      i   => i(4),
      nq  => ni(4),
      vdd => vdd,
      vss => vss
   );

a2_alu_k2 : a2_x2
   port map (
      i0  => i(5),
      i1  => ni(4),
      q   => alu_k(2),
      vdd => vdd,
      vss => vss
   );

n1_i5 : inv_x1
   port map (
      i   => i(5),
      nq  => ni(5),
      vdd => vdd,
      vss => vss
   );

a3_alu_k3 : a3_x2
   port map (
      i0  => ni(5),
      i1  => i(4),
      i2  => i(3),
      q   => alu_k(3),
      vdd => vdd,
      vss => vss
   );

a2_alu_k4 : a2_x2
   port map (
      i0  => i(4),
      i1  => i(3),
      q   => alu_k4_0,
      vdd => vdd,
      vss => vss
   );

o2_alu_k4 : o2_x2
   port map (
      i0  => alu_k4_0,
      i1  => i(5),
      q   => alu_k(4),
      vdd => vdd,
      vss => vss
   );

no2_alu_p_0 : no2_x1
   port map (
      i0  => alu_np(0),
      i1  => alu_np(1),
      nq  => alu_p_0,
      vdd => vdd,
      vss => vss
   );

no2_alu_p_1 : no2_x1
   port map (
      i0  => alu_np(2),
      i1  => alu_np(3),
      nq  => alu_p_1,
      vdd => vdd,
      vss => vss
   );

na2_alu_p : na2_x1
   port map (
      i0  => alu_p_0,
      i1  => alu_p_1,
      nq  => core_np,
      vdd => vdd,
      vss => vss
   );

no2_alu_g_0 : no2_x1
   port map (
      i0  => alu_np(1),
      i1  => alu_ng(0),
      nq  => alu_g_0,
      vdd => vdd,
      vss => vss
   );

no2_alu_g_1 : no2_x1
   port map (
      i0  => alu_np(3),
      i1  => alu_np(2),
      nq  => alu_g_1,
      vdd => vdd,
      vss => vss
   );

n1_alu_g_2 : inv_x1
   port map (
      i   => alu_ng(1),
      nq  => alu_g_2,
      vdd => vdd,
      vss => vss
   );

noa3_alu_g_3 : noa22_x1
   port map (
      i0  => alu_np(3),
      i1  => alu_ng(2),
      i2  => alu_ng(3),
      nq  => alu_g_3,
      vdd => vdd,
      vss => vss
   );

n1_alu_g_4 : inv_x1
   port map (
      i   => alu_g_3,
      nq  => alu_g_4,
      vdd => vdd,
      vss => vss
   );

na2_alu_g_5 : na2_x1
   port map (
      i0  => alu_g_0,
      i1  => alu_g_1,
      nq  => alu_g_5,
      vdd => vdd,
      vss => vss
   );

na2_alu_g_6 : na2_x1
   port map (
      i0  => alu_g_1,
      i1  => alu_g_2,
      nq  => alu_g_6,
      vdd => vdd,
      vss => vss
   );

na3_alu_g_7 : a3_x2
   port map (
      i0  => alu_g_4,
      i1  => alu_g_5,
      i2  => alu_g_6,
      q   => core_ng,
      vdd => vdd,
      vss => vss
   );

no2_alu_zero_0 : no2_x1
   port map (
      i0  => alu_f(0),
      i1  => alu_f(1),
      nq  => alu_zero_0,
      vdd => vdd,
      vss => vss
   );

no2_alu_zero_1 : no2_x1
   port map (
      i0  => alu_f(2),
      i1  => alu_f(3),
      nq  => alu_zero_1,
      vdd => vdd,
      vss => vss
   );

a2_alu_zero : a2_x2
   port map (
      i0  => alu_zero_0,
      i1  => alu_zero_1,
      q   => core_zero,
      vdd => vdd,
      vss => vss
   );

nxr2_alu_nover : xr2_x1
   port map (
      i0  => alu_over,
      i1  => alu_cout,
      q   => core_over,
      vdd => vdd,
      vss => vss
   );

n1_i6 : inv_x1
   port map (
      i   => i(8),
      nq  => ni(6),
      vdd => vdd,
      vss => vss
   );

nao3_acc_wen : noa22_x1
   port map (
      i0  => ni(6),
      i1  => i(7),
      i2  => i(6),
      nq  => acc_wen,
      vdd => vdd,
      vss => vss
   );

na2_ram_sh0 : na2_x1
   port map (
      i0  => i(8),
      i1  => i(7),
      nq  => ram_sh(0),
      vdd => vdd,
      vss => vss
   );

n1_ram_sh1 : inv_x1
   port map (
      i   => i(8),
      nq  => ram_sh(1),
      vdd => vdd,
      vss => vss
   );

a2_core_sh_left : a2_x2
   port map (
      i0  => i(8),
      i1  => i(7),
      q   => core_sh_left,
      vdd => vdd,
      vss => vss
   );

a2_core_sh_right : a2_x2
   port map (
      i0  => i(8),
      i1  => ni(3),
      q   => core_sh_right,
      vdd => vdd,
      vss => vss
   );

n1_ram_nwri_0 : inv_x1
   port map (
      i   => core_fonc,
      nq  => core_nfonc,
      vdd => vdd,
      vss => vss
   );

no2_ram_nwri_1 : no2_x1
   port map (
      i0  => core_test,
      i1  => core_nfonc,
      nq  => fonc_mode,
      vdd => vdd,
      vss => vss
   );

noa3_ram_nwri_2 : noa22_x1
   port map (
      i0  => i(8),
      i1  => i(7),
      i2  => fonc_mode,
      nq  => ram_nwri,
      vdd => vdd,
      vss => vss
   );

inv_ram_wri : inv_x1
   port map (
      i   => ram_nwri,
      nq  => ram_wri,
      vdd => vdd,
      vss => vss
   );

inv_noe : inv_x1
   port map (
      i   => noe,
      nq  => oe,
      vdd => vdd,
      vss => vss
   );


end structural;
