--description comportementale additionneur et accumulateur 4bits

--declaration interface

entity addac is 
port ( a : in bit_vector (3 downto 0);
       b : in bit_vector (3 downto 0);
     sel : in bit;
      ck : in bit;
     vdd : in bit;
     vss : in bit;
       s : inout bit_vector (3 downto 0)
     );
end addac;

--declaration architecture

architecture data_flow of addac is

signal mux_out : bit_vector (3 downto 0);
signal reg     : reg_vector (3 downto 0) register ;
signal carry   : bit_vector (3 downto 0);
signal reg_out : bit_vector (3 downto 0);

begin 

 with sel select
      mux_out <= a after 2 ns when '0',
                 reg_out after 2 ns when '1';

s <= b xor mux_out xor (carry ( 2 downto 0) & '0') after 4 ns;

carry <= (b and mux_out) or (b and (carry ( 2 downto 0) & '0')) 
         or (mux_out and (carry (2 downto 0) & '0'));

 writeaccu : block(ck='1' and not ck 'stable)
     begin 
       reg     <= guarded s ;
     end block ;

reg_out <= reg after 3 ns;
end data_flow;
   
