;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.6.0 #4309 (Oct 16 2006)
; This file generated Mon Oct 16 04:04:23 2006
;--------------------------------------------------------
	.module _atol
	.optsdcc -mds400 --model-flat24
	
;--------------------------------------------------------
; CPU specific extensions
;--------------------------------------------------------
.flat24 on		; 24 bit flat addressing
dpl1	=	0x84
dph1	=	0x85
dps	=	0x86
dpx	=	0x93
dpx1	=	0x95
esp	=	0x9B
ap	=	0x9C
_ap	=	0x9C
mcnt0	=	0xD1
mcnt1	=	0xD2
ma	=	0xD3
mb	=	0xD4
mc	=	0xD5
F1	=	0xD1	; user flag
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl _atol
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
;--------------------------------------------------------
; special function bits
;--------------------------------------------------------
;--------------------------------------------------------
; overlayable register banks
;--------------------------------------------------------
	.area REG_BANK_0	(REL,OVR,DATA)
	.ds 8
	.area REG_BANK_3	(REL,OVR,DATA)
	.ds 8
;--------------------------------------------------------
; internal ram data
;--------------------------------------------------------
	.area DSEG    (DATA)
_atol_rv_1_1:
	.ds 4
;--------------------------------------------------------
; overlayable items in internal ram 
;--------------------------------------------------------
	.area OSEG    (OVR,DATA)
;--------------------------------------------------------
; indirectly addressable internal ram data
;--------------------------------------------------------
	.area ISEG    (DATA)
;--------------------------------------------------------
; bit data
;--------------------------------------------------------
	.area BSEG    (BIT)
;--------------------------------------------------------
; paged external ram data
;--------------------------------------------------------
	.area PSEG    (PAG,XDATA)
;--------------------------------------------------------
; external ram data
;--------------------------------------------------------
	.area XSEG    (XDATA)
_atol_sloc1_1_0:
	.ds 4
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG   (XDATA)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area HOME    (CODE)
	.area GSINIT  (CODE)
	.area GSFINAL (CODE)
	.area GSINIT  (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME    (CODE)
	.area CSEG    (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG    (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function 'atol'
;------------------------------------------------------------
;rv                        Allocated with name '_atol_rv_1_1'
;sign                      Allocated to registers r0 
;s                         Allocated to registers r2 r3 r4 r5 
;sloc0                     Allocated with name '_atol_sloc0_1_0'
;sloc1                     Allocated with name '_atol_sloc1_1_0'
;------------------------------------------------------------
;	_atol.c:25: long atol(char * s)
;	genFunction
;	-----------------------------------------
;	 function atol
;	-----------------------------------------
_atol:
	ar2 = 0x02
	ar3 = 0x03
	ar4 = 0x04
	ar5 = 0x05
	ar6 = 0x06
	ar7 = 0x07
	ar0 = 0x00
	ar1 = 0x01
;	genReceive
	mov	r2,dpl
	mov	r3,dph
	mov	r4,dpx
	mov	r5,b
;	_atol.c:27: register long rv=0; 
;	genAssign
;	genAssign: resultIsFar = FALSE
	clr	a
	mov	_atol_rv_1_1,a
	mov	(_atol_rv_1_1 + 1),a
	mov	(_atol_rv_1_1 + 2),a
	mov	(_atol_rv_1_1 + 3),a
;	_atol.c:31: while (*s) {
;	genAssign
;	genAssign: resultIsFar = FALSE
	mov	ar6,r2
	mov	ar7,r3
	mov	ar0,r4
	mov	ar1,r5
;	genLabel
00107$:
;	genPointerGet
;	genGenPointerGet
	mov	dpl,r6
	mov	dph,r7
	mov	dpx,r0
	mov	b,r1
	lcall	__gptrget
;	genIfx
; Peephole 105   removed redundant mov
	mov  r2,a
;	genIfxJump
; Peephole 110   removed ljmp by inverse jump logic
	jz  00133$
00135$:
;	_atol.c:32: if (*s <= '9' && *s >= '0')
;	genCmpGt
;	genCmp
	clr	c
; Peephole 159   avoided xrl during execution
	mov  a,#(0x39 ^ 0x80)
	mov	b,r2
	xrl	b,#0x80
	subb	a,b
;	genIfxJump
; Peephole 132   changed ljmp to sjmp
; Peephole 160   removed sjmp by inverse jump logic
	jc   00102$
00136$:
;	genCmpLt
;	genCmp
	clr	c
	mov	a,r2
	xrl	a,#0x80
	subb	a,#0xB0
;	genIfxJump
; Peephole 108   removed ljmp by inverse jump logic
	jnc  00133$
00137$:
;	_atol.c:33: break;
;	genLabel
00102$:
;	_atol.c:34: if (*s == '-' || *s == '+') 
;	genPointerGet
;	genGenPointerGet
	mov	dpl,r6
	mov	dph,r7
	mov	dpx,r0
	mov	b,r1
	lcall	__gptrget
;	genCmpEq
;	gencjneshort
; Peephole 105   removed redundant mov
	mov  r2,a
	cjne	a,#0x2D,00138$
; Peephole 132   changed ljmp to sjmp
	sjmp 00133$
00138$:
;	genCmpEq
;	gencjneshort
	mov	a,r2
	cjne	a,#0x2B,00139$
; Peephole 132   changed ljmp to sjmp
	sjmp 00133$
00139$:
;	_atol.c:36: s++;
;	genPlus
	inc	r6
	cjne	r6,#0,00140$
	inc	r7
	cjne	r7,#0,00140$
	inc	r0
00140$:
;	did genPlusIncr
;	genGoto
;	genLabel
; Peephole 132   changed ljmp to sjmp
	sjmp 00107$
00133$:
;	genAssign
;	genAssign: resultIsFar = TRUE
	mov	ar2,r6
	mov	ar3,r7
	mov	ar4,r0
	mov	ar5,r1
;	_atol.c:39: sign = (*s == '-');
;	genPointerGet
;	genGenPointerGet
	mov	dpl,r6
	mov	dph,r7
	mov	dpx,r0
	mov	b,r1
	lcall	__gptrget
;	genCmpEq
;	gencjne
;	gencjneshort
; Peephole 105   removed redundant mov
	mov  r6,a
	cjne	a,#0x2D,00141$
	mov	a,#1
	sjmp	00142$
00141$:
	clr	a
00142$:
;	genAssign
;	genAssign: resultIsFar = FALSE
;	_atol.c:40: if (*s == '-' || *s == '+') s++;
;	genIfx
; Peephole 166   removed redundant mov
	mov  r7,a
	mov  ar0,r7 
;	genIfxJump
; Peephole 109   removed ljmp by inverse jump logic
	jnz  00110$
00143$:
;	genCmpEq
;	gencjneshort
	mov	a,r6
; Peephole 132   changed ljmp to sjmp
; Peephole 199   optimized misc jump sequence
	cjne a,#0x2B,00131$
;00144$:
; Peephole 200   removed redundant sjmp
00145$:
;	genLabel
00110$:
;	genPlus
	inc	r2
	cjne	r2,#0,00146$
	inc	r3
	cjne	r3,#0,00146$
	inc	r4
00146$:
;	did genPlusIncr
;	_atol.c:42: while (*s && *s >= '0' && *s <= '9') {
;	genLabel
00131$:
;	genAssign
;	genAssign: resultIsFar = TRUE
	mov	dptr,#_atol_sloc1_1_0
	mov	a,r2
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
	inc	dptr
	mov	a,r4
	movx	@dptr,a
	inc	dptr
	mov	a,r5
	movx	@dptr,a
;	genLabel
00115$:
;	genPointerGet
;	genGenPointerGet
	mov     dps, #1
	mov     dptr, #_atol_sloc1_1_0
	movx	a,@dptr
	mov	dpl,a
	inc	dptr
	movx	a,@dptr
	mov	dph,a
	inc	dptr
	movx	a,@dptr
	mov	dpx,a
	inc	dptr
	movx	a,@dptr
	mov	b,a
	mov	dps,#0
	lcall	__gptrget
;	genIfx
; Peephole 105   removed redundant mov
	mov  r6,a
;	genIfxJump
	jnz	00147$
	ljmp	00117$
00147$:
;	genCmpLt
;	genCmp
	clr	c
	mov	a,r6
	xrl	a,#0x80
	subb	a,#0xB0
;	genIfxJump
; Peephole 132   changed ljmp to sjmp
; Peephole 160   removed sjmp by inverse jump logic
	jc   00117$
00148$:
;	genCmpGt
;	genCmp
	clr	c
; Peephole 159   avoided xrl during execution
	mov  a,#(0x39 ^ 0x80)
	mov	b,r6
	xrl	b,#0x80
	subb	a,b
;	genIfxJump
; Peephole 132   changed ljmp to sjmp
; Peephole 160   removed sjmp by inverse jump logic
	jc   00117$
00149$:
;	_atol.c:43: rv = (rv * 10) + (*s - '0');
;	genIpush
	push	ar0
;	genAssign
;	genAssign: resultIsFar = TRUE
	mov	dptr,#__mullong_PARM_2
	mov	a,#0x0A
	movx	@dptr,a
	clr	a
	inc	dptr
	movx	@dptr,a
	inc	dptr
	movx	@dptr,a
	inc	dptr
	movx	@dptr,a
;	genCall
	push	ar6
;	genSend argreg = 1, size = 4 
	mov	dpl,_atol_rv_1_1
	mov	dph,(_atol_rv_1_1 + 1)
	mov	dpx,(_atol_rv_1_1 + 2)
	mov	b,(_atol_rv_1_1 + 3)
	lcall	__mullong
	mov	r7,dpl
	mov	r1,dph
	mov	r0,dpx
	mov	r2,b
	pop	ar6
;	genCast
	mov	a,r6
	rlc	a
	subb	a,acc
	mov	r3,a
;	genMinus
	mov	a,r6
	add	a,#0xD0
	mov	r6,a
	mov	a,r3
	addc	a,#0xFF
;	genCast
; Peephole 105   removed redundant mov
	mov  r3,a
	rlc	a
	subb	a,acc
	mov	r4,a
	mov	r5,a
;	genPlus
	mov	a,r6
	add	a,r7
	mov	_atol_rv_1_1,a
	mov	a,r3
	addc	a,r1
	mov	(_atol_rv_1_1 + 1),a
	mov	a,r4
	addc	a,r0
	mov	(_atol_rv_1_1 + 2),a
	mov	a,r5
	addc	a,r2
	mov	(_atol_rv_1_1 + 3),a
;	_atol.c:44: s++;
;	genPlus
	mov	dptr,#_atol_sloc1_1_0
;	Swapped plus args.
	movx	a,@dptr
	add	a,#0x01
	movx	@dptr,a
	inc	dptr
	movx	a,@dptr
	addc	a,#0x00
	movx	@dptr,a
	inc	dptr
	movx	a,@dptr
	addc	a,#0x00
	movx	@dptr,a
	inc	dptr
	movx	a,@dptr
	movx	@dptr,a
;	genIpop
	pop	ar0
;	genGoto
	ljmp	00115$
;	genLabel
00117$:
;	_atol.c:47: return (sign ? -rv : rv);
;	genIfx
	mov	a,r0
;	genIfxJump
; Peephole 110   removed ljmp by inverse jump logic
	jz  00120$
00150$:
;	genUminus
	clr	c
	clr	a
	subb	a,_atol_rv_1_1
	mov	r2,a
	clr	a
	subb	a,(_atol_rv_1_1 + 1)
	mov	r3,a
	clr	a
	subb	a,(_atol_rv_1_1 + 2)
	mov	r4,a
	clr	a
	subb	a,(_atol_rv_1_1 + 3)
	mov	r5,a
;	genGoto
;	genLabel
; Peephole 132   changed ljmp to sjmp
	sjmp 00121$
00120$:
;	genAssign
;	genAssign: resultIsFar = FALSE
	mov	r2,_atol_rv_1_1
	mov	r3,(_atol_rv_1_1 + 1)
	mov	r4,(_atol_rv_1_1 + 2)
	mov	r5,(_atol_rv_1_1 + 3)
;	genLabel
00121$:
;	genRet
	mov	dpl,r2
	mov	dph,r3
	mov	dpx,r4
	mov	b,r5
;	genLabel
00118$:
;	genEndFunction
	ret
	.area CSEG    (CODE)
	.area CONST   (CODE)
	.area XINIT   (CODE)
