# This file was automatically generated by SWIG (http://www.swig.org).
# Version 1.3.31
#
# Don't modify this file, modify the SWIG interface instead.

import _usrp1
import new
new_instancemethod = new.instancemethod
try:
    _swig_property = property
except NameError:
    pass # Python < 2.2 doesn't have 'property'.
def _swig_setattr_nondynamic(self,class_type,name,value,static=1):
    if (name == "thisown"): return self.this.own(value)
    if (name == "this"):
        if type(value).__name__ == 'PySwigObject':
            self.__dict__[name] = value
            return
    method = class_type.__swig_setmethods__.get(name,None)
    if method: return method(self,value)
    if (not static) or hasattr(self,name):
        self.__dict__[name] = value
    else:
        raise AttributeError("You cannot add attributes to %s" % self)

def _swig_setattr(self,class_type,name,value):
    return _swig_setattr_nondynamic(self,class_type,name,value,0)

def _swig_getattr(self,class_type,name):
    if (name == "thisown"): return self.this.own()
    method = class_type.__swig_getmethods__.get(name,None)
    if method: return method(self)
    raise AttributeError,name

def _swig_repr(self):
    try: strthis = "proxy of " + self.this.__repr__()
    except: strthis = ""
    return "<%s.%s; %s >" % (self.__class__.__module__, self.__class__.__name__, strthis,)

import types
try:
    _object = types.ObjectType
    _newclass = 1
except AttributeError:
    class _object : pass
    _newclass = 0
del types


def _swig_setattr_nondynamic_method(set):
    def set_attr(self,name,value):
        if (name == "thisown"): return self.this.own(value)
        if hasattr(self,name) or (name == "this"):
            set(self,name,value)
        else:
            raise AttributeError("You cannot add attributes to %s" % self)
    return set_attr


SPI_FMT_xSB_MASK = _usrp1.SPI_FMT_xSB_MASK
SPI_FMT_LSB = _usrp1.SPI_FMT_LSB
SPI_FMT_MSB = _usrp1.SPI_FMT_MSB
SPI_FMT_HDR_MASK = _usrp1.SPI_FMT_HDR_MASK
SPI_FMT_HDR_0 = _usrp1.SPI_FMT_HDR_0
SPI_FMT_HDR_1 = _usrp1.SPI_FMT_HDR_1
SPI_FMT_HDR_2 = _usrp1.SPI_FMT_HDR_2
SPI_ENABLE_FPGA = _usrp1.SPI_ENABLE_FPGA
SPI_ENABLE_CODEC_A = _usrp1.SPI_ENABLE_CODEC_A
SPI_ENABLE_CODEC_B = _usrp1.SPI_ENABLE_CODEC_B
SPI_ENABLE_reserved = _usrp1.SPI_ENABLE_reserved
SPI_ENABLE_TX_A = _usrp1.SPI_ENABLE_TX_A
SPI_ENABLE_RX_A = _usrp1.SPI_ENABLE_RX_A
SPI_ENABLE_TX_B = _usrp1.SPI_ENABLE_TX_B
SPI_ENABLE_RX_B = _usrp1.SPI_ENABLE_RX_B
FPGA_MODE_NORMAL = _usrp1.FPGA_MODE_NORMAL
FPGA_MODE_LOOPBACK = _usrp1.FPGA_MODE_LOOPBACK
FPGA_MODE_COUNTING = _usrp1.FPGA_MODE_COUNTING
class usrp1_sink_base(object):
    """Proxy of C++ usrp1_sink_base class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    def __init__(self): raise AttributeError, "No constructor defined"
    __repr__ = _swig_repr
    __swig_destroy__ = _usrp1.delete_usrp1_sink_base
    __del__ = lambda self : None;
    def set_interp_rate(*args):
        """set_interp_rate(self, unsigned int rate) -> bool"""
        return _usrp1.usrp1_sink_base_set_interp_rate(*args)

    def set_nchannels(*args):
        """set_nchannels(self, int nchan) -> bool"""
        return _usrp1.usrp1_sink_base_set_nchannels(*args)

    def set_mux(*args):
        """set_mux(self, int mux) -> bool"""
        return _usrp1.usrp1_sink_base_set_mux(*args)

    def set_tx_freq(*args):
        """set_tx_freq(self, int channel, double freq) -> bool"""
        return _usrp1.usrp1_sink_base_set_tx_freq(*args)

    def set_verbose(*args):
        """set_verbose(self, bool verbose)"""
        return _usrp1.usrp1_sink_base_set_verbose(*args)

    def fpga_master_clock_freq(*args):
        """fpga_master_clock_freq(self) -> long"""
        return _usrp1.usrp1_sink_base_fpga_master_clock_freq(*args)

    def converter_rate(*args):
        """converter_rate(self) -> long"""
        return _usrp1.usrp1_sink_base_converter_rate(*args)

    def dac_rate(*args):
        """dac_rate(self) -> long"""
        return _usrp1.usrp1_sink_base_dac_rate(*args)

    def dac_freq(*args):
        """dac_freq(self) -> long"""
        return _usrp1.usrp1_sink_base_dac_freq(*args)

    def interp_rate(*args):
        """interp_rate(self) -> unsigned int"""
        return _usrp1.usrp1_sink_base_interp_rate(*args)

    def tx_freq(*args):
        """tx_freq(self, int channel) -> double"""
        return _usrp1.usrp1_sink_base_tx_freq(*args)

    def nunderruns(*args):
        """nunderruns(self) -> int"""
        return _usrp1.usrp1_sink_base_nunderruns(*args)

    def set_pga(*args):
        """set_pga(self, int which, double gain_in_db) -> bool"""
        return _usrp1.usrp1_sink_base_set_pga(*args)

    def pga(*args):
        """pga(self, int which) -> double"""
        return _usrp1.usrp1_sink_base_pga(*args)

    def pga_min(*args):
        """pga_min(self) -> double"""
        return _usrp1.usrp1_sink_base_pga_min(*args)

    def pga_max(*args):
        """pga_max(self) -> double"""
        return _usrp1.usrp1_sink_base_pga_max(*args)

    def pga_db_per_step(*args):
        """pga_db_per_step(self) -> double"""
        return _usrp1.usrp1_sink_base_pga_db_per_step(*args)

    def daughterboard_id(*args):
        """daughterboard_id(self, int which_dboard) -> int"""
        return _usrp1.usrp1_sink_base_daughterboard_id(*args)

    def set_adc_offset(*args):
        """set_adc_offset(self, int which, int offset) -> bool"""
        return _usrp1.usrp1_sink_base_set_adc_offset(*args)

    def set_dac_offset(*args):
        """set_dac_offset(self, int which, int offset, int offset_pin) -> bool"""
        return _usrp1.usrp1_sink_base_set_dac_offset(*args)

    def set_adc_buffer_bypass(*args):
        """set_adc_buffer_bypass(self, int which, bool bypass) -> bool"""
        return _usrp1.usrp1_sink_base_set_adc_buffer_bypass(*args)

    def serial_number(*args):
        """serial_number(self) -> string"""
        return _usrp1.usrp1_sink_base_serial_number(*args)

    def _write_oe(*args):
        """_write_oe(self, int which_dboard, int value, int mask) -> bool"""
        return _usrp1.usrp1_sink_base__write_oe(*args)

    def write_io(*args):
        """write_io(self, int which_dboard, int value, int mask) -> bool"""
        return _usrp1.usrp1_sink_base_write_io(*args)

    def read_io(*args):
        """read_io(self, int which_dboard) -> int"""
        return _usrp1.usrp1_sink_base_read_io(*args)

    def write_aux_dac(*args):
        """write_aux_dac(self, int which_dboard, int which_dac, int value) -> bool"""
        return _usrp1.usrp1_sink_base_write_aux_dac(*args)

    def read_aux_adc(*args):
        """read_aux_adc(self, int which_dboard, int which_adc) -> int"""
        return _usrp1.usrp1_sink_base_read_aux_adc(*args)

    def write_eeprom(*args):
        """write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) -> bool"""
        return _usrp1.usrp1_sink_base_write_eeprom(*args)

    def read_eeprom(*args):
        """read_eeprom(self, int i2c_addr, int eeprom_offset, int len) -> string"""
        return _usrp1.usrp1_sink_base_read_eeprom(*args)

    def write_i2c(*args):
        """write_i2c(self, int i2c_addr, string buf) -> bool"""
        return _usrp1.usrp1_sink_base_write_i2c(*args)

    def read_i2c(*args):
        """read_i2c(self, int i2c_addr, int len) -> string"""
        return _usrp1.usrp1_sink_base_read_i2c(*args)

    def _write_fpga_reg(*args):
        """_write_fpga_reg(self, int regno, int value) -> bool"""
        return _usrp1.usrp1_sink_base__write_fpga_reg(*args)

    def _read_fpga_reg(*args):
        """_read_fpga_reg(self, int regno) -> int"""
        return _usrp1.usrp1_sink_base__read_fpga_reg(*args)

    def _write_9862(*args):
        """_write_9862(self, int which_codec, int regno, unsigned char value) -> bool"""
        return _usrp1.usrp1_sink_base__write_9862(*args)

    def _read_9862(*args):
        """_read_9862(self, int which_codec, int regno) -> int"""
        return _usrp1.usrp1_sink_base__read_9862(*args)

    def _write_spi(*args):
        """_write_spi(self, int optional_header, int enables, int format, string buf) -> bool"""
        return _usrp1.usrp1_sink_base__write_spi(*args)

    def _read_spi(*args):
        """_read_spi(self, int optional_header, int enables, int format, int len) -> string"""
        return _usrp1.usrp1_sink_base__read_spi(*args)

usrp1_sink_base_swigregister = _usrp1.usrp1_sink_base_swigregister
usrp1_sink_base_swigregister(usrp1_sink_base)

class usrp1_source_base(object):
    """Proxy of C++ usrp1_source_base class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    def __init__(self): raise AttributeError, "No constructor defined"
    __repr__ = _swig_repr
    __swig_destroy__ = _usrp1.delete_usrp1_source_base
    __del__ = lambda self : None;
    def set_decim_rate(*args):
        """set_decim_rate(self, unsigned int rate) -> bool"""
        return _usrp1.usrp1_source_base_set_decim_rate(*args)

    def set_nchannels(*args):
        """set_nchannels(self, int nchan) -> bool"""
        return _usrp1.usrp1_source_base_set_nchannels(*args)

    def set_mux(*args):
        """set_mux(self, int mux) -> bool"""
        return _usrp1.usrp1_source_base_set_mux(*args)

    def set_rx_freq(*args):
        """set_rx_freq(self, int channel, double freq) -> bool"""
        return _usrp1.usrp1_source_base_set_rx_freq(*args)

    def set_fpga_mode(*args):
        """set_fpga_mode(self, int mode) -> bool"""
        return _usrp1.usrp1_source_base_set_fpga_mode(*args)

    def set_ddc_phase(*args):
        """set_ddc_phase(self, int channel, int phase) -> bool"""
        return _usrp1.usrp1_source_base_set_ddc_phase(*args)

    def set_verbose(*args):
        """set_verbose(self, bool verbose)"""
        return _usrp1.usrp1_source_base_set_verbose(*args)

    def fpga_master_clock_freq(*args):
        """fpga_master_clock_freq(self) -> long"""
        return _usrp1.usrp1_source_base_fpga_master_clock_freq(*args)

    def converter_rate(*args):
        """converter_rate(self) -> long"""
        return _usrp1.usrp1_source_base_converter_rate(*args)

    def adc_rate(*args):
        """adc_rate(self) -> long"""
        return _usrp1.usrp1_source_base_adc_rate(*args)

    def adc_freq(*args):
        """adc_freq(self) -> long"""
        return _usrp1.usrp1_source_base_adc_freq(*args)

    def decim_rate(*args):
        """decim_rate(self) -> unsigned int"""
        return _usrp1.usrp1_source_base_decim_rate(*args)

    def rx_freq(*args):
        """rx_freq(self, int channel) -> double"""
        return _usrp1.usrp1_source_base_rx_freq(*args)

    def noverruns(*args):
        """noverruns(self) -> int"""
        return _usrp1.usrp1_source_base_noverruns(*args)

    def set_pga(*args):
        """set_pga(self, int which, double gain_in_db) -> bool"""
        return _usrp1.usrp1_source_base_set_pga(*args)

    def pga(*args):
        """pga(self, int which) -> double"""
        return _usrp1.usrp1_source_base_pga(*args)

    def pga_min(*args):
        """pga_min(self) -> double"""
        return _usrp1.usrp1_source_base_pga_min(*args)

    def pga_max(*args):
        """pga_max(self) -> double"""
        return _usrp1.usrp1_source_base_pga_max(*args)

    def pga_db_per_step(*args):
        """pga_db_per_step(self) -> double"""
        return _usrp1.usrp1_source_base_pga_db_per_step(*args)

    def daughterboard_id(*args):
        """daughterboard_id(self, int which_dboard) -> int"""
        return _usrp1.usrp1_source_base_daughterboard_id(*args)

    def set_adc_offset(*args):
        """set_adc_offset(self, int which, int offset) -> bool"""
        return _usrp1.usrp1_source_base_set_adc_offset(*args)

    def set_dac_offset(*args):
        """set_dac_offset(self, int which, int offset, int offset_pin) -> bool"""
        return _usrp1.usrp1_source_base_set_dac_offset(*args)

    def set_adc_buffer_bypass(*args):
        """set_adc_buffer_bypass(self, int which, bool bypass) -> bool"""
        return _usrp1.usrp1_source_base_set_adc_buffer_bypass(*args)

    def serial_number(*args):
        """serial_number(self) -> string"""
        return _usrp1.usrp1_source_base_serial_number(*args)

    def _write_oe(*args):
        """_write_oe(self, int which_dboard, int value, int mask) -> bool"""
        return _usrp1.usrp1_source_base__write_oe(*args)

    def write_io(*args):
        """write_io(self, int which_dboard, int value, int mask) -> bool"""
        return _usrp1.usrp1_source_base_write_io(*args)

    def read_io(*args):
        """read_io(self, int which_dboard) -> int"""
        return _usrp1.usrp1_source_base_read_io(*args)

    def set_dc_offset_cl_enable(*args):
        """set_dc_offset_cl_enable(self, int bits, int mask) -> bool"""
        return _usrp1.usrp1_source_base_set_dc_offset_cl_enable(*args)

    def set_format(*args):
        """set_format(self, unsigned int format) -> bool"""
        return _usrp1.usrp1_source_base_set_format(*args)

    def format(*args):
        """format(self) -> unsigned int"""
        return _usrp1.usrp1_source_base_format(*args)

    def make_format(*args):
        """
        make_format(int width=16, int shift=0, bool want_q=True, bool bypass_halfband=False) -> unsigned int
        make_format(int width=16, int shift=0, bool want_q=True) -> unsigned int
        make_format(int width=16, int shift=0) -> unsigned int
        make_format(int width=16) -> unsigned int
        make_format() -> unsigned int
        """
        return _usrp1.usrp1_source_base_make_format(*args)

    make_format = staticmethod(make_format)
    def format_width(*args):
        """format_width(unsigned int format) -> int"""
        return _usrp1.usrp1_source_base_format_width(*args)

    format_width = staticmethod(format_width)
    def format_shift(*args):
        """format_shift(unsigned int format) -> int"""
        return _usrp1.usrp1_source_base_format_shift(*args)

    format_shift = staticmethod(format_shift)
    def format_want_q(*args):
        """format_want_q(unsigned int format) -> bool"""
        return _usrp1.usrp1_source_base_format_want_q(*args)

    format_want_q = staticmethod(format_want_q)
    def format_bypass_halfband(*args):
        """format_bypass_halfband(unsigned int format) -> bool"""
        return _usrp1.usrp1_source_base_format_bypass_halfband(*args)

    format_bypass_halfband = staticmethod(format_bypass_halfband)
    def write_aux_dac(*args):
        """write_aux_dac(self, int which_dboard, int which_dac, int value) -> bool"""
        return _usrp1.usrp1_source_base_write_aux_dac(*args)

    def read_aux_adc(*args):
        """read_aux_adc(self, int which_dboard, int which_adc) -> int"""
        return _usrp1.usrp1_source_base_read_aux_adc(*args)

    def write_eeprom(*args):
        """write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) -> bool"""
        return _usrp1.usrp1_source_base_write_eeprom(*args)

    def read_eeprom(*args):
        """read_eeprom(self, int i2c_addr, int eeprom_offset, int len) -> string"""
        return _usrp1.usrp1_source_base_read_eeprom(*args)

    def write_i2c(*args):
        """write_i2c(self, int i2c_addr, string buf) -> bool"""
        return _usrp1.usrp1_source_base_write_i2c(*args)

    def read_i2c(*args):
        """read_i2c(self, int i2c_addr, int len) -> string"""
        return _usrp1.usrp1_source_base_read_i2c(*args)

    def _write_fpga_reg(*args):
        """_write_fpga_reg(self, int regno, int value) -> bool"""
        return _usrp1.usrp1_source_base__write_fpga_reg(*args)

    def _write_fpga_reg_masked(*args):
        """_write_fpga_reg_masked(self, int regno, int value, int mask) -> bool"""
        return _usrp1.usrp1_source_base__write_fpga_reg_masked(*args)

    def _read_fpga_reg(*args):
        """_read_fpga_reg(self, int regno) -> int"""
        return _usrp1.usrp1_source_base__read_fpga_reg(*args)

    def _write_9862(*args):
        """_write_9862(self, int which_codec, int regno, unsigned char value) -> bool"""
        return _usrp1.usrp1_source_base__write_9862(*args)

    def _read_9862(*args):
        """_read_9862(self, int which_codec, int regno) -> int"""
        return _usrp1.usrp1_source_base__read_9862(*args)

    def _write_spi(*args):
        """_write_spi(self, int optional_header, int enables, int format, string buf) -> bool"""
        return _usrp1.usrp1_source_base__write_spi(*args)

    def _read_spi(*args):
        """_read_spi(self, int optional_header, int enables, int format, int len) -> string"""
        return _usrp1.usrp1_source_base__read_spi(*args)

usrp1_source_base_swigregister = _usrp1.usrp1_source_base_swigregister
usrp1_source_base_swigregister(usrp1_source_base)

def usrp1_source_base_make_format(*args):
  """
    make_format(int width=16, int shift=0, bool want_q=True, bool bypass_halfband=False) -> unsigned int
    make_format(int width=16, int shift=0, bool want_q=True) -> unsigned int
    make_format(int width=16, int shift=0) -> unsigned int
    make_format(int width=16) -> unsigned int
    usrp1_source_base_make_format() -> unsigned int
    """
  return _usrp1.usrp1_source_base_make_format(*args)

def usrp1_source_base_format_width(*args):
  """usrp1_source_base_format_width(unsigned int format) -> int"""
  return _usrp1.usrp1_source_base_format_width(*args)

def usrp1_source_base_format_shift(*args):
  """usrp1_source_base_format_shift(unsigned int format) -> int"""
  return _usrp1.usrp1_source_base_format_shift(*args)

def usrp1_source_base_format_want_q(*args):
  """usrp1_source_base_format_want_q(unsigned int format) -> bool"""
  return _usrp1.usrp1_source_base_format_want_q(*args)

def usrp1_source_base_format_bypass_halfband(*args):
  """usrp1_source_base_format_bypass_halfband(unsigned int format) -> bool"""
  return _usrp1.usrp1_source_base_format_bypass_halfband(*args)

class usrp1_sink_c_sptr(object):
    """Proxy of C++ usrp1_sink_c_sptr class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    def __init__(self, *args): 
        """
        __init__(self) -> usrp1_sink_c_sptr
        __init__(self,  p) -> usrp1_sink_c_sptr
        """
        this = _usrp1.new_usrp1_sink_c_sptr(*args)
        try: self.this.append(this)
        except: self.this = this
    def __deref__(*args):
        """__deref__(self)"""
        return _usrp1.usrp1_sink_c_sptr___deref__(*args)

    __swig_destroy__ = _usrp1.delete_usrp1_sink_c_sptr
    __del__ = lambda self : None;
    def set_interp_rate(*args):
        """set_interp_rate(self, unsigned int rate) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_set_interp_rate(*args)

    def set_nchannels(*args):
        """set_nchannels(self, int nchan) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_set_nchannels(*args)

    def set_mux(*args):
        """set_mux(self, int mux) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_set_mux(*args)

    def set_tx_freq(*args):
        """set_tx_freq(self, int channel, double freq) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_set_tx_freq(*args)

    def set_verbose(*args):
        """set_verbose(self, bool verbose)"""
        return _usrp1.usrp1_sink_c_sptr_set_verbose(*args)

    def fpga_master_clock_freq(*args):
        """fpga_master_clock_freq(self) -> long"""
        return _usrp1.usrp1_sink_c_sptr_fpga_master_clock_freq(*args)

    def converter_rate(*args):
        """converter_rate(self) -> long"""
        return _usrp1.usrp1_sink_c_sptr_converter_rate(*args)

    def dac_rate(*args):
        """dac_rate(self) -> long"""
        return _usrp1.usrp1_sink_c_sptr_dac_rate(*args)

    def dac_freq(*args):
        """dac_freq(self) -> long"""
        return _usrp1.usrp1_sink_c_sptr_dac_freq(*args)

    def interp_rate(*args):
        """interp_rate(self) -> unsigned int"""
        return _usrp1.usrp1_sink_c_sptr_interp_rate(*args)

    def tx_freq(*args):
        """tx_freq(self, int channel) -> double"""
        return _usrp1.usrp1_sink_c_sptr_tx_freq(*args)

    def nunderruns(*args):
        """nunderruns(self) -> int"""
        return _usrp1.usrp1_sink_c_sptr_nunderruns(*args)

    def set_pga(*args):
        """set_pga(self, int which, double gain_in_db) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_set_pga(*args)

    def pga(*args):
        """pga(self, int which) -> double"""
        return _usrp1.usrp1_sink_c_sptr_pga(*args)

    def pga_min(*args):
        """pga_min(self) -> double"""
        return _usrp1.usrp1_sink_c_sptr_pga_min(*args)

    def pga_max(*args):
        """pga_max(self) -> double"""
        return _usrp1.usrp1_sink_c_sptr_pga_max(*args)

    def pga_db_per_step(*args):
        """pga_db_per_step(self) -> double"""
        return _usrp1.usrp1_sink_c_sptr_pga_db_per_step(*args)

    def daughterboard_id(*args):
        """daughterboard_id(self, int which_dboard) -> int"""
        return _usrp1.usrp1_sink_c_sptr_daughterboard_id(*args)

    def set_adc_offset(*args):
        """set_adc_offset(self, int which, int offset) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_set_adc_offset(*args)

    def set_dac_offset(*args):
        """set_dac_offset(self, int which, int offset, int offset_pin) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_set_dac_offset(*args)

    def set_adc_buffer_bypass(*args):
        """set_adc_buffer_bypass(self, int which, bool bypass) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_set_adc_buffer_bypass(*args)

    def serial_number(*args):
        """serial_number(self) -> string"""
        return _usrp1.usrp1_sink_c_sptr_serial_number(*args)

    def _write_oe(*args):
        """_write_oe(self, int which_dboard, int value, int mask) -> bool"""
        return _usrp1.usrp1_sink_c_sptr__write_oe(*args)

    def write_io(*args):
        """write_io(self, int which_dboard, int value, int mask) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_write_io(*args)

    def read_io(*args):
        """read_io(self, int which_dboard) -> int"""
        return _usrp1.usrp1_sink_c_sptr_read_io(*args)

    def write_aux_dac(*args):
        """write_aux_dac(self, int which_dboard, int which_dac, int value) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_write_aux_dac(*args)

    def read_aux_adc(*args):
        """read_aux_adc(self, int which_dboard, int which_adc) -> int"""
        return _usrp1.usrp1_sink_c_sptr_read_aux_adc(*args)

    def write_eeprom(*args):
        """write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_write_eeprom(*args)

    def read_eeprom(*args):
        """read_eeprom(self, int i2c_addr, int eeprom_offset, int len) -> string"""
        return _usrp1.usrp1_sink_c_sptr_read_eeprom(*args)

    def write_i2c(*args):
        """write_i2c(self, int i2c_addr, string buf) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_write_i2c(*args)

    def read_i2c(*args):
        """read_i2c(self, int i2c_addr, int len) -> string"""
        return _usrp1.usrp1_sink_c_sptr_read_i2c(*args)

    def _write_fpga_reg(*args):
        """_write_fpga_reg(self, int regno, int value) -> bool"""
        return _usrp1.usrp1_sink_c_sptr__write_fpga_reg(*args)

    def _read_fpga_reg(*args):
        """_read_fpga_reg(self, int regno) -> int"""
        return _usrp1.usrp1_sink_c_sptr__read_fpga_reg(*args)

    def _write_9862(*args):
        """_write_9862(self, int which_codec, int regno, unsigned char value) -> bool"""
        return _usrp1.usrp1_sink_c_sptr__write_9862(*args)

    def _read_9862(*args):
        """_read_9862(self, int which_codec, int regno) -> int"""
        return _usrp1.usrp1_sink_c_sptr__read_9862(*args)

    def _write_spi(*args):
        """_write_spi(self, int optional_header, int enables, int format, string buf) -> bool"""
        return _usrp1.usrp1_sink_c_sptr__write_spi(*args)

    def _read_spi(*args):
        """_read_spi(self, int optional_header, int enables, int format, int len) -> string"""
        return _usrp1.usrp1_sink_c_sptr__read_spi(*args)

    def name(*args):
        """name(self) -> string"""
        return _usrp1.usrp1_sink_c_sptr_name(*args)

    def input_signature(*args):
        """input_signature(self) -> gr_io_signature_sptr"""
        return _usrp1.usrp1_sink_c_sptr_input_signature(*args)

    def output_signature(*args):
        """output_signature(self) -> gr_io_signature_sptr"""
        return _usrp1.usrp1_sink_c_sptr_output_signature(*args)

    def unique_id(*args):
        """unique_id(self) -> long"""
        return _usrp1.usrp1_sink_c_sptr_unique_id(*args)

    def history(*args):
        """history(self) -> unsigned int"""
        return _usrp1.usrp1_sink_c_sptr_history(*args)

    def output_multiple(*args):
        """output_multiple(self) -> int"""
        return _usrp1.usrp1_sink_c_sptr_output_multiple(*args)

    def relative_rate(*args):
        """relative_rate(self) -> double"""
        return _usrp1.usrp1_sink_c_sptr_relative_rate(*args)

    def check_topology(*args):
        """check_topology(self, int ninputs, int noutputs) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_check_topology(*args)

    def start(*args):
        """start(self) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_start(*args)

    def stop(*args):
        """stop(self) -> bool"""
        return _usrp1.usrp1_sink_c_sptr_stop(*args)

    def detail(*args):
        """detail(self) -> gr_block_detail_sptr"""
        return _usrp1.usrp1_sink_c_sptr_detail(*args)

    def set_detail(*args):
        """set_detail(self, gr_block_detail_sptr detail)"""
        return _usrp1.usrp1_sink_c_sptr_set_detail(*args)

usrp1_sink_c_sptr_swigregister = _usrp1.usrp1_sink_c_sptr_swigregister
usrp1_sink_c_sptr_swigregister(usrp1_sink_c_sptr)


def usrp1_sink_c_block(*args):
  """usrp1_sink_c_block(usrp1_sink_c_sptr r) -> gr_block_sptr"""
  return _usrp1.usrp1_sink_c_block(*args)
usrp1_sink_c_sptr.block = lambda self: usrp1_sink_c_block (self)
usrp1_sink_c_sptr.__repr__ = lambda self: "<gr_block %s (%d)>" % (self.name(), self.unique_id ())


def sink_c(*args):
  """
    sink_c(int which_board, unsigned int interp_rate, int nchan, 
        int mux, int fusb_block_size, int fusb_nblocks, 
        string fpga_filename, string firmware_filename) -> usrp1_sink_c_sptr
    """
  return _usrp1.sink_c(*args)
class usrp1_sink_s_sptr(object):
    """Proxy of C++ usrp1_sink_s_sptr class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    def __init__(self, *args): 
        """
        __init__(self) -> usrp1_sink_s_sptr
        __init__(self,  p) -> usrp1_sink_s_sptr
        """
        this = _usrp1.new_usrp1_sink_s_sptr(*args)
        try: self.this.append(this)
        except: self.this = this
    def __deref__(*args):
        """__deref__(self)"""
        return _usrp1.usrp1_sink_s_sptr___deref__(*args)

    __swig_destroy__ = _usrp1.delete_usrp1_sink_s_sptr
    __del__ = lambda self : None;
    def set_interp_rate(*args):
        """set_interp_rate(self, unsigned int rate) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_set_interp_rate(*args)

    def set_nchannels(*args):
        """set_nchannels(self, int nchan) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_set_nchannels(*args)

    def set_mux(*args):
        """set_mux(self, int mux) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_set_mux(*args)

    def set_tx_freq(*args):
        """set_tx_freq(self, int channel, double freq) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_set_tx_freq(*args)

    def set_verbose(*args):
        """set_verbose(self, bool verbose)"""
        return _usrp1.usrp1_sink_s_sptr_set_verbose(*args)

    def fpga_master_clock_freq(*args):
        """fpga_master_clock_freq(self) -> long"""
        return _usrp1.usrp1_sink_s_sptr_fpga_master_clock_freq(*args)

    def converter_rate(*args):
        """converter_rate(self) -> long"""
        return _usrp1.usrp1_sink_s_sptr_converter_rate(*args)

    def dac_rate(*args):
        """dac_rate(self) -> long"""
        return _usrp1.usrp1_sink_s_sptr_dac_rate(*args)

    def dac_freq(*args):
        """dac_freq(self) -> long"""
        return _usrp1.usrp1_sink_s_sptr_dac_freq(*args)

    def interp_rate(*args):
        """interp_rate(self) -> unsigned int"""
        return _usrp1.usrp1_sink_s_sptr_interp_rate(*args)

    def tx_freq(*args):
        """tx_freq(self, int channel) -> double"""
        return _usrp1.usrp1_sink_s_sptr_tx_freq(*args)

    def nunderruns(*args):
        """nunderruns(self) -> int"""
        return _usrp1.usrp1_sink_s_sptr_nunderruns(*args)

    def set_pga(*args):
        """set_pga(self, int which, double gain_in_db) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_set_pga(*args)

    def pga(*args):
        """pga(self, int which) -> double"""
        return _usrp1.usrp1_sink_s_sptr_pga(*args)

    def pga_min(*args):
        """pga_min(self) -> double"""
        return _usrp1.usrp1_sink_s_sptr_pga_min(*args)

    def pga_max(*args):
        """pga_max(self) -> double"""
        return _usrp1.usrp1_sink_s_sptr_pga_max(*args)

    def pga_db_per_step(*args):
        """pga_db_per_step(self) -> double"""
        return _usrp1.usrp1_sink_s_sptr_pga_db_per_step(*args)

    def daughterboard_id(*args):
        """daughterboard_id(self, int which_dboard) -> int"""
        return _usrp1.usrp1_sink_s_sptr_daughterboard_id(*args)

    def set_adc_offset(*args):
        """set_adc_offset(self, int which, int offset) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_set_adc_offset(*args)

    def set_dac_offset(*args):
        """set_dac_offset(self, int which, int offset, int offset_pin) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_set_dac_offset(*args)

    def set_adc_buffer_bypass(*args):
        """set_adc_buffer_bypass(self, int which, bool bypass) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_set_adc_buffer_bypass(*args)

    def serial_number(*args):
        """serial_number(self) -> string"""
        return _usrp1.usrp1_sink_s_sptr_serial_number(*args)

    def _write_oe(*args):
        """_write_oe(self, int which_dboard, int value, int mask) -> bool"""
        return _usrp1.usrp1_sink_s_sptr__write_oe(*args)

    def write_io(*args):
        """write_io(self, int which_dboard, int value, int mask) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_write_io(*args)

    def read_io(*args):
        """read_io(self, int which_dboard) -> int"""
        return _usrp1.usrp1_sink_s_sptr_read_io(*args)

    def write_aux_dac(*args):
        """write_aux_dac(self, int which_dboard, int which_dac, int value) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_write_aux_dac(*args)

    def read_aux_adc(*args):
        """read_aux_adc(self, int which_dboard, int which_adc) -> int"""
        return _usrp1.usrp1_sink_s_sptr_read_aux_adc(*args)

    def write_eeprom(*args):
        """write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_write_eeprom(*args)

    def read_eeprom(*args):
        """read_eeprom(self, int i2c_addr, int eeprom_offset, int len) -> string"""
        return _usrp1.usrp1_sink_s_sptr_read_eeprom(*args)

    def write_i2c(*args):
        """write_i2c(self, int i2c_addr, string buf) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_write_i2c(*args)

    def read_i2c(*args):
        """read_i2c(self, int i2c_addr, int len) -> string"""
        return _usrp1.usrp1_sink_s_sptr_read_i2c(*args)

    def _write_fpga_reg(*args):
        """_write_fpga_reg(self, int regno, int value) -> bool"""
        return _usrp1.usrp1_sink_s_sptr__write_fpga_reg(*args)

    def _read_fpga_reg(*args):
        """_read_fpga_reg(self, int regno) -> int"""
        return _usrp1.usrp1_sink_s_sptr__read_fpga_reg(*args)

    def _write_9862(*args):
        """_write_9862(self, int which_codec, int regno, unsigned char value) -> bool"""
        return _usrp1.usrp1_sink_s_sptr__write_9862(*args)

    def _read_9862(*args):
        """_read_9862(self, int which_codec, int regno) -> int"""
        return _usrp1.usrp1_sink_s_sptr__read_9862(*args)

    def _write_spi(*args):
        """_write_spi(self, int optional_header, int enables, int format, string buf) -> bool"""
        return _usrp1.usrp1_sink_s_sptr__write_spi(*args)

    def _read_spi(*args):
        """_read_spi(self, int optional_header, int enables, int format, int len) -> string"""
        return _usrp1.usrp1_sink_s_sptr__read_spi(*args)

    def name(*args):
        """name(self) -> string"""
        return _usrp1.usrp1_sink_s_sptr_name(*args)

    def input_signature(*args):
        """input_signature(self) -> gr_io_signature_sptr"""
        return _usrp1.usrp1_sink_s_sptr_input_signature(*args)

    def output_signature(*args):
        """output_signature(self) -> gr_io_signature_sptr"""
        return _usrp1.usrp1_sink_s_sptr_output_signature(*args)

    def unique_id(*args):
        """unique_id(self) -> long"""
        return _usrp1.usrp1_sink_s_sptr_unique_id(*args)

    def history(*args):
        """history(self) -> unsigned int"""
        return _usrp1.usrp1_sink_s_sptr_history(*args)

    def output_multiple(*args):
        """output_multiple(self) -> int"""
        return _usrp1.usrp1_sink_s_sptr_output_multiple(*args)

    def relative_rate(*args):
        """relative_rate(self) -> double"""
        return _usrp1.usrp1_sink_s_sptr_relative_rate(*args)

    def check_topology(*args):
        """check_topology(self, int ninputs, int noutputs) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_check_topology(*args)

    def start(*args):
        """start(self) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_start(*args)

    def stop(*args):
        """stop(self) -> bool"""
        return _usrp1.usrp1_sink_s_sptr_stop(*args)

    def detail(*args):
        """detail(self) -> gr_block_detail_sptr"""
        return _usrp1.usrp1_sink_s_sptr_detail(*args)

    def set_detail(*args):
        """set_detail(self, gr_block_detail_sptr detail)"""
        return _usrp1.usrp1_sink_s_sptr_set_detail(*args)

usrp1_sink_s_sptr_swigregister = _usrp1.usrp1_sink_s_sptr_swigregister
usrp1_sink_s_sptr_swigregister(usrp1_sink_s_sptr)


def usrp1_sink_s_block(*args):
  """usrp1_sink_s_block(usrp1_sink_s_sptr r) -> gr_block_sptr"""
  return _usrp1.usrp1_sink_s_block(*args)
usrp1_sink_s_sptr.block = lambda self: usrp1_sink_s_block (self)
usrp1_sink_s_sptr.__repr__ = lambda self: "<gr_block %s (%d)>" % (self.name(), self.unique_id ())


def sink_s(*args):
  """
    sink_s(int which_board, unsigned int interp_rate, int nchan, 
        int mux, int fusb_block_size, int fusb_nblocks, 
        string fpga_filename, string firmware_filename) -> usrp1_sink_s_sptr
    """
  return _usrp1.sink_s(*args)
class usrp1_source_c_sptr(object):
    """Proxy of C++ usrp1_source_c_sptr class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    def __init__(self, *args): 
        """
        __init__(self) -> usrp1_source_c_sptr
        __init__(self,  p) -> usrp1_source_c_sptr
        """
        this = _usrp1.new_usrp1_source_c_sptr(*args)
        try: self.this.append(this)
        except: self.this = this
    def __deref__(*args):
        """__deref__(self)"""
        return _usrp1.usrp1_source_c_sptr___deref__(*args)

    __swig_destroy__ = _usrp1.delete_usrp1_source_c_sptr
    __del__ = lambda self : None;
    def set_decim_rate(*args):
        """set_decim_rate(self, unsigned int rate) -> bool"""
        return _usrp1.usrp1_source_c_sptr_set_decim_rate(*args)

    def set_nchannels(*args):
        """set_nchannels(self, int nchan) -> bool"""
        return _usrp1.usrp1_source_c_sptr_set_nchannels(*args)

    def set_mux(*args):
        """set_mux(self, int mux) -> bool"""
        return _usrp1.usrp1_source_c_sptr_set_mux(*args)

    def set_rx_freq(*args):
        """set_rx_freq(self, int channel, double freq) -> bool"""
        return _usrp1.usrp1_source_c_sptr_set_rx_freq(*args)

    def set_fpga_mode(*args):
        """set_fpga_mode(self, int mode) -> bool"""
        return _usrp1.usrp1_source_c_sptr_set_fpga_mode(*args)

    def set_ddc_phase(*args):
        """set_ddc_phase(self, int channel, int phase) -> bool"""
        return _usrp1.usrp1_source_c_sptr_set_ddc_phase(*args)

    def set_verbose(*args):
        """set_verbose(self, bool verbose)"""
        return _usrp1.usrp1_source_c_sptr_set_verbose(*args)

    def fpga_master_clock_freq(*args):
        """fpga_master_clock_freq(self) -> long"""
        return _usrp1.usrp1_source_c_sptr_fpga_master_clock_freq(*args)

    def converter_rate(*args):
        """converter_rate(self) -> long"""
        return _usrp1.usrp1_source_c_sptr_converter_rate(*args)

    def adc_rate(*args):
        """adc_rate(self) -> long"""
        return _usrp1.usrp1_source_c_sptr_adc_rate(*args)

    def adc_freq(*args):
        """adc_freq(self) -> long"""
        return _usrp1.usrp1_source_c_sptr_adc_freq(*args)

    def decim_rate(*args):
        """decim_rate(self) -> unsigned int"""
        return _usrp1.usrp1_source_c_sptr_decim_rate(*args)

    def rx_freq(*args):
        """rx_freq(self, int channel) -> double"""
        return _usrp1.usrp1_source_c_sptr_rx_freq(*args)

    def noverruns(*args):
        """noverruns(self) -> int"""
        return _usrp1.usrp1_source_c_sptr_noverruns(*args)

    def set_pga(*args):
        """set_pga(self, int which, double gain_in_db) -> bool"""
        return _usrp1.usrp1_source_c_sptr_set_pga(*args)

    def pga(*args):
        """pga(self, int which) -> double"""
        return _usrp1.usrp1_source_c_sptr_pga(*args)

    def pga_min(*args):
        """pga_min(self) -> double"""
        return _usrp1.usrp1_source_c_sptr_pga_min(*args)

    def pga_max(*args):
        """pga_max(self) -> double"""
        return _usrp1.usrp1_source_c_sptr_pga_max(*args)

    def pga_db_per_step(*args):
        """pga_db_per_step(self) -> double"""
        return _usrp1.usrp1_source_c_sptr_pga_db_per_step(*args)

    def daughterboard_id(*args):
        """daughterboard_id(self, int which_dboard) -> int"""
        return _usrp1.usrp1_source_c_sptr_daughterboard_id(*args)

    def set_adc_offset(*args):
        """set_adc_offset(self, int which, int offset) -> bool"""
        return _usrp1.usrp1_source_c_sptr_set_adc_offset(*args)

    def set_dac_offset(*args):
        """set_dac_offset(self, int which, int offset, int offset_pin) -> bool"""
        return _usrp1.usrp1_source_c_sptr_set_dac_offset(*args)

    def set_adc_buffer_bypass(*args):
        """set_adc_buffer_bypass(self, int which, bool bypass) -> bool"""
        return _usrp1.usrp1_source_c_sptr_set_adc_buffer_bypass(*args)

    def serial_number(*args):
        """serial_number(self) -> string"""
        return _usrp1.usrp1_source_c_sptr_serial_number(*args)

    def _write_oe(*args):
        """_write_oe(self, int which_dboard, int value, int mask) -> bool"""
        return _usrp1.usrp1_source_c_sptr__write_oe(*args)

    def write_io(*args):
        """write_io(self, int which_dboard, int value, int mask) -> bool"""
        return _usrp1.usrp1_source_c_sptr_write_io(*args)

    def read_io(*args):
        """read_io(self, int which_dboard) -> int"""
        return _usrp1.usrp1_source_c_sptr_read_io(*args)

    def set_dc_offset_cl_enable(*args):
        """set_dc_offset_cl_enable(self, int bits, int mask) -> bool"""
        return _usrp1.usrp1_source_c_sptr_set_dc_offset_cl_enable(*args)

    def set_format(*args):
        """set_format(self, unsigned int format) -> bool"""
        return _usrp1.usrp1_source_c_sptr_set_format(*args)

    def format(*args):
        """format(self) -> unsigned int"""
        return _usrp1.usrp1_source_c_sptr_format(*args)

    def make_format(*args):
        """
        make_format(self, int width=16, int shift=0, bool want_q=True, bool bypass_halfband=False) -> unsigned int
        make_format(self, int width=16, int shift=0, bool want_q=True) -> unsigned int
        make_format(self, int width=16, int shift=0) -> unsigned int
        make_format(self, int width=16) -> unsigned int
        make_format(self) -> unsigned int
        """
        return _usrp1.usrp1_source_c_sptr_make_format(*args)

    def format_width(*args):
        """format_width(self, unsigned int format) -> int"""
        return _usrp1.usrp1_source_c_sptr_format_width(*args)

    def format_shift(*args):
        """format_shift(self, unsigned int format) -> int"""
        return _usrp1.usrp1_source_c_sptr_format_shift(*args)

    def format_want_q(*args):
        """format_want_q(self, unsigned int format) -> bool"""
        return _usrp1.usrp1_source_c_sptr_format_want_q(*args)

    def format_bypass_halfband(*args):
        """format_bypass_halfband(self, unsigned int format) -> bool"""
        return _usrp1.usrp1_source_c_sptr_format_bypass_halfband(*args)

    def write_aux_dac(*args):
        """write_aux_dac(self, int which_dboard, int which_dac, int value) -> bool"""
        return _usrp1.usrp1_source_c_sptr_write_aux_dac(*args)

    def read_aux_adc(*args):
        """read_aux_adc(self, int which_dboard, int which_adc) -> int"""
        return _usrp1.usrp1_source_c_sptr_read_aux_adc(*args)

    def write_eeprom(*args):
        """write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) -> bool"""
        return _usrp1.usrp1_source_c_sptr_write_eeprom(*args)

    def read_eeprom(*args):
        """read_eeprom(self, int i2c_addr, int eeprom_offset, int len) -> string"""
        return _usrp1.usrp1_source_c_sptr_read_eeprom(*args)

    def write_i2c(*args):
        """write_i2c(self, int i2c_addr, string buf) -> bool"""
        return _usrp1.usrp1_source_c_sptr_write_i2c(*args)

    def read_i2c(*args):
        """read_i2c(self, int i2c_addr, int len) -> string"""
        return _usrp1.usrp1_source_c_sptr_read_i2c(*args)

    def _write_fpga_reg(*args):
        """_write_fpga_reg(self, int regno, int value) -> bool"""
        return _usrp1.usrp1_source_c_sptr__write_fpga_reg(*args)

    def _write_fpga_reg_masked(*args):
        """_write_fpga_reg_masked(self, int regno, int value, int mask) -> bool"""
        return _usrp1.usrp1_source_c_sptr__write_fpga_reg_masked(*args)

    def _read_fpga_reg(*args):
        """_read_fpga_reg(self, int regno) -> int"""
        return _usrp1.usrp1_source_c_sptr__read_fpga_reg(*args)

    def _write_9862(*args):
        """_write_9862(self, int which_codec, int regno, unsigned char value) -> bool"""
        return _usrp1.usrp1_source_c_sptr__write_9862(*args)

    def _read_9862(*args):
        """_read_9862(self, int which_codec, int regno) -> int"""
        return _usrp1.usrp1_source_c_sptr__read_9862(*args)

    def _write_spi(*args):
        """_write_spi(self, int optional_header, int enables, int format, string buf) -> bool"""
        return _usrp1.usrp1_source_c_sptr__write_spi(*args)

    def _read_spi(*args):
        """_read_spi(self, int optional_header, int enables, int format, int len) -> string"""
        return _usrp1.usrp1_source_c_sptr__read_spi(*args)

    def name(*args):
        """name(self) -> string"""
        return _usrp1.usrp1_source_c_sptr_name(*args)

    def input_signature(*args):
        """input_signature(self) -> gr_io_signature_sptr"""
        return _usrp1.usrp1_source_c_sptr_input_signature(*args)

    def output_signature(*args):
        """output_signature(self) -> gr_io_signature_sptr"""
        return _usrp1.usrp1_source_c_sptr_output_signature(*args)

    def unique_id(*args):
        """unique_id(self) -> long"""
        return _usrp1.usrp1_source_c_sptr_unique_id(*args)

    def history(*args):
        """history(self) -> unsigned int"""
        return _usrp1.usrp1_source_c_sptr_history(*args)

    def output_multiple(*args):
        """output_multiple(self) -> int"""
        return _usrp1.usrp1_source_c_sptr_output_multiple(*args)

    def relative_rate(*args):
        """relative_rate(self) -> double"""
        return _usrp1.usrp1_source_c_sptr_relative_rate(*args)

    def check_topology(*args):
        """check_topology(self, int ninputs, int noutputs) -> bool"""
        return _usrp1.usrp1_source_c_sptr_check_topology(*args)

    def start(*args):
        """start(self) -> bool"""
        return _usrp1.usrp1_source_c_sptr_start(*args)

    def stop(*args):
        """stop(self) -> bool"""
        return _usrp1.usrp1_source_c_sptr_stop(*args)

    def detail(*args):
        """detail(self) -> gr_block_detail_sptr"""
        return _usrp1.usrp1_source_c_sptr_detail(*args)

    def set_detail(*args):
        """set_detail(self, gr_block_detail_sptr detail)"""
        return _usrp1.usrp1_source_c_sptr_set_detail(*args)

usrp1_source_c_sptr_swigregister = _usrp1.usrp1_source_c_sptr_swigregister
usrp1_source_c_sptr_swigregister(usrp1_source_c_sptr)


def usrp1_source_c_block(*args):
  """usrp1_source_c_block(usrp1_source_c_sptr r) -> gr_block_sptr"""
  return _usrp1.usrp1_source_c_block(*args)
usrp1_source_c_sptr.block = lambda self: usrp1_source_c_block (self)
usrp1_source_c_sptr.__repr__ = lambda self: "<gr_block %s (%d)>" % (self.name(), self.unique_id ())


def source_c(*args):
  """
    source_c(int which_board, unsigned int decim_rate, int nchan, 
        int mux, int mode, int fusb_block_size, int fusb_nblocks, 
        string fpga_filename, string firmware_filename) -> usrp1_source_c_sptr
    """
  return _usrp1.source_c(*args)
class usrp1_source_s_sptr(object):
    """Proxy of C++ usrp1_source_s_sptr class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    def __init__(self, *args): 
        """
        __init__(self) -> usrp1_source_s_sptr
        __init__(self,  p) -> usrp1_source_s_sptr
        """
        this = _usrp1.new_usrp1_source_s_sptr(*args)
        try: self.this.append(this)
        except: self.this = this
    def __deref__(*args):
        """__deref__(self)"""
        return _usrp1.usrp1_source_s_sptr___deref__(*args)

    __swig_destroy__ = _usrp1.delete_usrp1_source_s_sptr
    __del__ = lambda self : None;
    def set_decim_rate(*args):
        """set_decim_rate(self, unsigned int rate) -> bool"""
        return _usrp1.usrp1_source_s_sptr_set_decim_rate(*args)

    def set_nchannels(*args):
        """set_nchannels(self, int nchan) -> bool"""
        return _usrp1.usrp1_source_s_sptr_set_nchannels(*args)

    def set_mux(*args):
        """set_mux(self, int mux) -> bool"""
        return _usrp1.usrp1_source_s_sptr_set_mux(*args)

    def set_rx_freq(*args):
        """set_rx_freq(self, int channel, double freq) -> bool"""
        return _usrp1.usrp1_source_s_sptr_set_rx_freq(*args)

    def set_fpga_mode(*args):
        """set_fpga_mode(self, int mode) -> bool"""
        return _usrp1.usrp1_source_s_sptr_set_fpga_mode(*args)

    def set_ddc_phase(*args):
        """set_ddc_phase(self, int channel, int phase) -> bool"""
        return _usrp1.usrp1_source_s_sptr_set_ddc_phase(*args)

    def set_verbose(*args):
        """set_verbose(self, bool verbose)"""
        return _usrp1.usrp1_source_s_sptr_set_verbose(*args)

    def fpga_master_clock_freq(*args):
        """fpga_master_clock_freq(self) -> long"""
        return _usrp1.usrp1_source_s_sptr_fpga_master_clock_freq(*args)

    def converter_rate(*args):
        """converter_rate(self) -> long"""
        return _usrp1.usrp1_source_s_sptr_converter_rate(*args)

    def adc_rate(*args):
        """adc_rate(self) -> long"""
        return _usrp1.usrp1_source_s_sptr_adc_rate(*args)

    def adc_freq(*args):
        """adc_freq(self) -> long"""
        return _usrp1.usrp1_source_s_sptr_adc_freq(*args)

    def decim_rate(*args):
        """decim_rate(self) -> unsigned int"""
        return _usrp1.usrp1_source_s_sptr_decim_rate(*args)

    def rx_freq(*args):
        """rx_freq(self, int channel) -> double"""
        return _usrp1.usrp1_source_s_sptr_rx_freq(*args)

    def noverruns(*args):
        """noverruns(self) -> int"""
        return _usrp1.usrp1_source_s_sptr_noverruns(*args)

    def set_pga(*args):
        """set_pga(self, int which, double gain_in_db) -> bool"""
        return _usrp1.usrp1_source_s_sptr_set_pga(*args)

    def pga(*args):
        """pga(self, int which) -> double"""
        return _usrp1.usrp1_source_s_sptr_pga(*args)

    def pga_min(*args):
        """pga_min(self) -> double"""
        return _usrp1.usrp1_source_s_sptr_pga_min(*args)

    def pga_max(*args):
        """pga_max(self) -> double"""
        return _usrp1.usrp1_source_s_sptr_pga_max(*args)

    def pga_db_per_step(*args):
        """pga_db_per_step(self) -> double"""
        return _usrp1.usrp1_source_s_sptr_pga_db_per_step(*args)

    def daughterboard_id(*args):
        """daughterboard_id(self, int which_dboard) -> int"""
        return _usrp1.usrp1_source_s_sptr_daughterboard_id(*args)

    def set_adc_offset(*args):
        """set_adc_offset(self, int which, int offset) -> bool"""
        return _usrp1.usrp1_source_s_sptr_set_adc_offset(*args)

    def set_dac_offset(*args):
        """set_dac_offset(self, int which, int offset, int offset_pin) -> bool"""
        return _usrp1.usrp1_source_s_sptr_set_dac_offset(*args)

    def set_adc_buffer_bypass(*args):
        """set_adc_buffer_bypass(self, int which, bool bypass) -> bool"""
        return _usrp1.usrp1_source_s_sptr_set_adc_buffer_bypass(*args)

    def serial_number(*args):
        """serial_number(self) -> string"""
        return _usrp1.usrp1_source_s_sptr_serial_number(*args)

    def _write_oe(*args):
        """_write_oe(self, int which_dboard, int value, int mask) -> bool"""
        return _usrp1.usrp1_source_s_sptr__write_oe(*args)

    def write_io(*args):
        """write_io(self, int which_dboard, int value, int mask) -> bool"""
        return _usrp1.usrp1_source_s_sptr_write_io(*args)

    def read_io(*args):
        """read_io(self, int which_dboard) -> int"""
        return _usrp1.usrp1_source_s_sptr_read_io(*args)

    def set_dc_offset_cl_enable(*args):
        """set_dc_offset_cl_enable(self, int bits, int mask) -> bool"""
        return _usrp1.usrp1_source_s_sptr_set_dc_offset_cl_enable(*args)

    def set_format(*args):
        """set_format(self, unsigned int format) -> bool"""
        return _usrp1.usrp1_source_s_sptr_set_format(*args)

    def format(*args):
        """format(self) -> unsigned int"""
        return _usrp1.usrp1_source_s_sptr_format(*args)

    def make_format(*args):
        """
        make_format(self, int width=16, int shift=0, bool want_q=True, bool bypass_halfband=False) -> unsigned int
        make_format(self, int width=16, int shift=0, bool want_q=True) -> unsigned int
        make_format(self, int width=16, int shift=0) -> unsigned int
        make_format(self, int width=16) -> unsigned int
        make_format(self) -> unsigned int
        """
        return _usrp1.usrp1_source_s_sptr_make_format(*args)

    def format_width(*args):
        """format_width(self, unsigned int format) -> int"""
        return _usrp1.usrp1_source_s_sptr_format_width(*args)

    def format_shift(*args):
        """format_shift(self, unsigned int format) -> int"""
        return _usrp1.usrp1_source_s_sptr_format_shift(*args)

    def format_want_q(*args):
        """format_want_q(self, unsigned int format) -> bool"""
        return _usrp1.usrp1_source_s_sptr_format_want_q(*args)

    def format_bypass_halfband(*args):
        """format_bypass_halfband(self, unsigned int format) -> bool"""
        return _usrp1.usrp1_source_s_sptr_format_bypass_halfband(*args)

    def write_aux_dac(*args):
        """write_aux_dac(self, int which_dboard, int which_dac, int value) -> bool"""
        return _usrp1.usrp1_source_s_sptr_write_aux_dac(*args)

    def read_aux_adc(*args):
        """read_aux_adc(self, int which_dboard, int which_adc) -> int"""
        return _usrp1.usrp1_source_s_sptr_read_aux_adc(*args)

    def write_eeprom(*args):
        """write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) -> bool"""
        return _usrp1.usrp1_source_s_sptr_write_eeprom(*args)

    def read_eeprom(*args):
        """read_eeprom(self, int i2c_addr, int eeprom_offset, int len) -> string"""
        return _usrp1.usrp1_source_s_sptr_read_eeprom(*args)

    def write_i2c(*args):
        """write_i2c(self, int i2c_addr, string buf) -> bool"""
        return _usrp1.usrp1_source_s_sptr_write_i2c(*args)

    def read_i2c(*args):
        """read_i2c(self, int i2c_addr, int len) -> string"""
        return _usrp1.usrp1_source_s_sptr_read_i2c(*args)

    def _write_fpga_reg(*args):
        """_write_fpga_reg(self, int regno, int value) -> bool"""
        return _usrp1.usrp1_source_s_sptr__write_fpga_reg(*args)

    def _write_fpga_reg_masked(*args):
        """_write_fpga_reg_masked(self, int regno, int value, int mask) -> bool"""
        return _usrp1.usrp1_source_s_sptr__write_fpga_reg_masked(*args)

    def _read_fpga_reg(*args):
        """_read_fpga_reg(self, int regno) -> int"""
        return _usrp1.usrp1_source_s_sptr__read_fpga_reg(*args)

    def _write_9862(*args):
        """_write_9862(self, int which_codec, int regno, unsigned char value) -> bool"""
        return _usrp1.usrp1_source_s_sptr__write_9862(*args)

    def _read_9862(*args):
        """_read_9862(self, int which_codec, int regno) -> int"""
        return _usrp1.usrp1_source_s_sptr__read_9862(*args)

    def _write_spi(*args):
        """_write_spi(self, int optional_header, int enables, int format, string buf) -> bool"""
        return _usrp1.usrp1_source_s_sptr__write_spi(*args)

    def _read_spi(*args):
        """_read_spi(self, int optional_header, int enables, int format, int len) -> string"""
        return _usrp1.usrp1_source_s_sptr__read_spi(*args)

    def name(*args):
        """name(self) -> string"""
        return _usrp1.usrp1_source_s_sptr_name(*args)

    def input_signature(*args):
        """input_signature(self) -> gr_io_signature_sptr"""
        return _usrp1.usrp1_source_s_sptr_input_signature(*args)

    def output_signature(*args):
        """output_signature(self) -> gr_io_signature_sptr"""
        return _usrp1.usrp1_source_s_sptr_output_signature(*args)

    def unique_id(*args):
        """unique_id(self) -> long"""
        return _usrp1.usrp1_source_s_sptr_unique_id(*args)

    def history(*args):
        """history(self) -> unsigned int"""
        return _usrp1.usrp1_source_s_sptr_history(*args)

    def output_multiple(*args):
        """output_multiple(self) -> int"""
        return _usrp1.usrp1_source_s_sptr_output_multiple(*args)

    def relative_rate(*args):
        """relative_rate(self) -> double"""
        return _usrp1.usrp1_source_s_sptr_relative_rate(*args)

    def check_topology(*args):
        """check_topology(self, int ninputs, int noutputs) -> bool"""
        return _usrp1.usrp1_source_s_sptr_check_topology(*args)

    def start(*args):
        """start(self) -> bool"""
        return _usrp1.usrp1_source_s_sptr_start(*args)

    def stop(*args):
        """stop(self) -> bool"""
        return _usrp1.usrp1_source_s_sptr_stop(*args)

    def detail(*args):
        """detail(self) -> gr_block_detail_sptr"""
        return _usrp1.usrp1_source_s_sptr_detail(*args)

    def set_detail(*args):
        """set_detail(self, gr_block_detail_sptr detail)"""
        return _usrp1.usrp1_source_s_sptr_set_detail(*args)

usrp1_source_s_sptr_swigregister = _usrp1.usrp1_source_s_sptr_swigregister
usrp1_source_s_sptr_swigregister(usrp1_source_s_sptr)


def usrp1_source_s_block(*args):
  """usrp1_source_s_block(usrp1_source_s_sptr r) -> gr_block_sptr"""
  return _usrp1.usrp1_source_s_block(*args)
usrp1_source_s_sptr.block = lambda self: usrp1_source_s_block (self)
usrp1_source_s_sptr.__repr__ = lambda self: "<gr_block %s (%d)>" % (self.name(), self.unique_id ())


def source_s(*args):
  """
    source_s(int which_board, unsigned int decim_rate, int nchan, 
        int mux, int mode, int fusb_block_size, int fusb_nblocks, 
        string fpga_filename, string firmware_filename) -> usrp1_source_s_sptr
    """
  return _usrp1.source_s(*args)


