Changes to the instruction set
==============================

1. The cc bit in ARITH ops have been removed.  The CC option
   is now merged with the arithmetic opcode.  I think this saves
   a bit of space since most of the time the cc bit is false.

2. The following V9 instructions have been added

        MULX
        SMULX
        DIVX
        SLLX
        SRLX
        SRAX
        LDX
        STX
        MOVcc  (* conditional moves on condition code *)
        FMOVcc (* conditional moves on condition code *)
        MOVR   (* conditional moves on integer condition *)
        BR     (* branch on integer register with prediction *)
        BP     (* branch on integer condition with prediction *)

   Not everything is generated by the instruction selection module yet.

New optimizations in the Sparc backend
======================================
1.  Strength reduction for multiply/division by a constant. 
2.  Propagation of annotations
3.  There is a flag is determines whether we should use BR instructions.
    These branch instructions branches on the value of an integer register.
4.  NOTB folding is implemented
