# This file was automatically generated by SWIG (http://www.swig.org).
# Version 1.3.40
#
# Do not make changes to this file unless you know what you are doing--modify
# the SWIG interface file instead.

from sys import version_info
if version_info >= (2,6,0):
    def swig_import_helper():
        from os.path import dirname
        import imp
        fp = None
        try:
            fp, pathname, description = imp.find_module('_usrp_swig', [dirname(__file__)])
        except ImportError:
            import _usrp_swig
            return _usrp_swig
        if fp is not None:
            try:
                _mod = imp.load_module('_usrp_swig', fp, pathname, description)
            finally:
                fp.close()
            return _mod
    _usrp_swig = swig_import_helper()
    del swig_import_helper
else:
    import _usrp_swig
del version_info
try:
    _swig_property = property
except NameError:
    pass # Python < 2.2 doesn't have 'property'.
def _swig_setattr_nondynamic(self,class_type,name,value,static=1):
    if (name == "thisown"): return self.this.own(value)
    if (name == "this"):
        if type(value).__name__ == 'SwigPyObject':
            self.__dict__[name] = value
            return
    method = class_type.__swig_setmethods__.get(name,None)
    if method: return method(self,value)
    if (not static) or hasattr(self,name):
        self.__dict__[name] = value
    else:
        raise AttributeError("You cannot add attributes to %s" % self)

def _swig_setattr(self,class_type,name,value):
    return _swig_setattr_nondynamic(self,class_type,name,value,0)

def _swig_getattr(self,class_type,name):
    if (name == "thisown"): return self.this.own()
    method = class_type.__swig_getmethods__.get(name,None)
    if method: return method(self)
    raise AttributeError(name)

def _swig_repr(self):
    try: strthis = "proxy of " + self.this.__repr__()
    except: strthis = ""
    return "<%s.%s; %s >" % (self.__class__.__module__, self.__class__.__name__, strthis,)

try:
    _object = object
    _newclass = 1
except AttributeError:
    class _object : pass
    _newclass = 0


def _swig_setattr_nondynamic_method(set):
    def set_attr(self,name,value):
        if (name == "thisown"): return self.this.own(value)
        if hasattr(self,name) or (name == "this"):
            set(self,name,value)
        else:
            raise AttributeError("You cannot add attributes to %s" % self)
    return set_attr


class SwigPyIterator(object):
    """Proxy of C++ swig::SwigPyIterator class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    def __init__(self, *args, **kwargs): raise AttributeError("No constructor defined - class is abstract")
    __repr__ = _swig_repr
    __swig_destroy__ = _usrp_swig.delete_SwigPyIterator
    __del__ = lambda self : None;
    def value(self):
        """value(self) -> PyObject"""
        return _usrp_swig.SwigPyIterator_value(self)

    def incr(self, n = 1):
        """incr(self, size_t n = 1) -> SwigPyIterator"""
        return _usrp_swig.SwigPyIterator_incr(self, n)

    def decr(self, n = 1):
        """decr(self, size_t n = 1) -> SwigPyIterator"""
        return _usrp_swig.SwigPyIterator_decr(self, n)

    def distance(self, *args, **kwargs):
        """distance(self, SwigPyIterator x) -> ptrdiff_t"""
        return _usrp_swig.SwigPyIterator_distance(self, *args, **kwargs)

    def equal(self, *args, **kwargs):
        """equal(self, SwigPyIterator x) -> bool"""
        return _usrp_swig.SwigPyIterator_equal(self, *args, **kwargs)

    def copy(self):
        """copy(self) -> SwigPyIterator"""
        return _usrp_swig.SwigPyIterator_copy(self)

    def next(self):
        """next(self) -> PyObject"""
        return _usrp_swig.SwigPyIterator_next(self)

    def __next__(self):
        """__next__(self) -> PyObject"""
        return _usrp_swig.SwigPyIterator___next__(self)

    def previous(self):
        """previous(self) -> PyObject"""
        return _usrp_swig.SwigPyIterator_previous(self)

    def advance(self, *args, **kwargs):
        """advance(self, ptrdiff_t n) -> SwigPyIterator"""
        return _usrp_swig.SwigPyIterator_advance(self, *args, **kwargs)

    def __eq__(self, *args, **kwargs):
        """__eq__(self, SwigPyIterator x) -> bool"""
        return _usrp_swig.SwigPyIterator___eq__(self, *args, **kwargs)

    def __ne__(self, *args, **kwargs):
        """__ne__(self, SwigPyIterator x) -> bool"""
        return _usrp_swig.SwigPyIterator___ne__(self, *args, **kwargs)

    def __iadd__(self, *args, **kwargs):
        """__iadd__(self, ptrdiff_t n) -> SwigPyIterator"""
        return _usrp_swig.SwigPyIterator___iadd__(self, *args, **kwargs)

    def __isub__(self, *args, **kwargs):
        """__isub__(self, ptrdiff_t n) -> SwigPyIterator"""
        return _usrp_swig.SwigPyIterator___isub__(self, *args, **kwargs)

    def __add__(self, *args, **kwargs):
        """__add__(self, ptrdiff_t n) -> SwigPyIterator"""
        return _usrp_swig.SwigPyIterator___add__(self, *args, **kwargs)

    def __sub__(self, *args):
        """
        __sub__(self, ptrdiff_t n) -> SwigPyIterator
        __sub__(self, SwigPyIterator x) -> ptrdiff_t
        """
        return _usrp_swig.SwigPyIterator___sub__(self, *args)

    def __iter__(self): return self
SwigPyIterator_swigregister = _usrp_swig.SwigPyIterator_swigregister
SwigPyIterator_swigregister(SwigPyIterator)

sizeof_char = _usrp_swig.sizeof_char
sizeof_short = _usrp_swig.sizeof_short
sizeof_int = _usrp_swig.sizeof_int
sizeof_float = _usrp_swig.sizeof_float
sizeof_double = _usrp_swig.sizeof_double
sizeof_gr_complex = _usrp_swig.sizeof_gr_complex
class usrp_subdev_spec(object):
    """Proxy of C++ usrp_subdev_spec class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    side = _swig_property(_usrp_swig.usrp_subdev_spec_side_get, _usrp_swig.usrp_subdev_spec_side_set)
    subdev = _swig_property(_usrp_swig.usrp_subdev_spec_subdev_get, _usrp_swig.usrp_subdev_spec_subdev_set)
    def __init__(self, _side = 0, _subdev = 0): 
        """__init__(self, unsigned int _side = 0, unsigned int _subdev = 0) -> usrp_subdev_spec"""
        this = _usrp_swig.new_usrp_subdev_spec(_side, _subdev)
        try: self.this.append(this)
        except: self.this = this
    __swig_destroy__ = _usrp_swig.delete_usrp_subdev_spec
    __del__ = lambda self : None;
usrp_subdev_spec_swigregister = _usrp_swig.usrp_subdev_spec_swigregister
usrp_subdev_spec_swigregister(usrp_subdev_spec)

class usrp_tune_result(object):
    """Proxy of C++ usrp_tune_result class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    def __init__(self, baseband = 0, dxc = 0, residual = 0, inv = 0): 
        """
        __init__(self, double baseband = 0, double dxc = 0, double residual = 0, 
            bool inv = 0) -> usrp_tune_result
        """
        this = _usrp_swig.new_usrp_tune_result(baseband, dxc, residual, inv)
        try: self.this.append(this)
        except: self.this = this
    __swig_destroy__ = _usrp_swig.delete_usrp_tune_result
    __del__ = lambda self : None;
    baseband_freq = _swig_property(_usrp_swig.usrp_tune_result_baseband_freq_get, _usrp_swig.usrp_tune_result_baseband_freq_set)
    dxc_freq = _swig_property(_usrp_swig.usrp_tune_result_dxc_freq_get, _usrp_swig.usrp_tune_result_dxc_freq_set)
    residual_freq = _swig_property(_usrp_swig.usrp_tune_result_residual_freq_get, _usrp_swig.usrp_tune_result_residual_freq_set)
    inverted = _swig_property(_usrp_swig.usrp_tune_result_inverted_get, _usrp_swig.usrp_tune_result_inverted_set)
usrp_tune_result_swigregister = _usrp_swig.usrp_tune_result_swigregister
usrp_tune_result_swigregister(usrp_tune_result)

class freq_result_t(object):
    """Proxy of C++ freq_result_t class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    ok = _swig_property(_usrp_swig.freq_result_t_ok_get, _usrp_swig.freq_result_t_ok_set)
    baseband_freq = _swig_property(_usrp_swig.freq_result_t_baseband_freq_get, _usrp_swig.freq_result_t_baseband_freq_set)
    def __init__(self): 
        """__init__(self) -> freq_result_t"""
        this = _usrp_swig.new_freq_result_t()
        try: self.this.append(this)
        except: self.this = this
    __swig_destroy__ = _usrp_swig.delete_freq_result_t
    __del__ = lambda self : None;
freq_result_t_swigregister = _usrp_swig.freq_result_t_swigregister
freq_result_t_swigregister(freq_result_t)

class db_base(object):
    """Proxy of C++ db_base class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    def __init__(self, *args, **kwargs): raise AttributeError("No constructor defined - class is abstract")
    __repr__ = _swig_repr
    __swig_destroy__ = _usrp_swig.delete_db_base
    __del__ = lambda self : None;
    def dbid(self):
        """dbid(self) -> int"""
        return _usrp_swig.db_base_dbid(self)

    def name(self):
        """name(self) -> string"""
        return _usrp_swig.db_base_name(self)

    def side_and_name(self):
        """side_and_name(self) -> string"""
        return _usrp_swig.db_base_side_and_name(self)

    def which(self):
        """which(self) -> int"""
        return _usrp_swig.db_base_which(self)

    def bypass_adc_buffers(self, *args, **kwargs):
        """bypass_adc_buffers(self, bool bypass) -> bool"""
        return _usrp_swig.db_base_bypass_adc_buffers(self, *args, **kwargs)

    def set_atr_mask(self, *args, **kwargs):
        """set_atr_mask(self, int v) -> bool"""
        return _usrp_swig.db_base_set_atr_mask(self, *args, **kwargs)

    def set_atr_txval(self, *args, **kwargs):
        """set_atr_txval(self, int v) -> bool"""
        return _usrp_swig.db_base_set_atr_txval(self, *args, **kwargs)

    def set_atr_rxval(self, *args, **kwargs):
        """set_atr_rxval(self, int v) -> bool"""
        return _usrp_swig.db_base_set_atr_rxval(self, *args, **kwargs)

    def set_atr_tx_delay(self, *args, **kwargs):
        """set_atr_tx_delay(self, int v) -> bool"""
        return _usrp_swig.db_base_set_atr_tx_delay(self, *args, **kwargs)

    def set_atr_rx_delay(self, *args, **kwargs):
        """set_atr_rx_delay(self, int v) -> bool"""
        return _usrp_swig.db_base_set_atr_rx_delay(self, *args, **kwargs)

    def set_lo_offset(self, *args, **kwargs):
        """set_lo_offset(self, double offset) -> bool"""
        return _usrp_swig.db_base_set_lo_offset(self, *args, **kwargs)

    def lo_offset(self):
        """lo_offset(self) -> double"""
        return _usrp_swig.db_base_lo_offset(self)

    def gain_min(self):
        """gain_min(self) -> float"""
        return _usrp_swig.db_base_gain_min(self)

    def gain_max(self):
        """gain_max(self) -> float"""
        return _usrp_swig.db_base_gain_max(self)

    def gain_db_per_step(self):
        """gain_db_per_step(self) -> float"""
        return _usrp_swig.db_base_gain_db_per_step(self)

    def freq_min(self):
        """freq_min(self) -> double"""
        return _usrp_swig.db_base_freq_min(self)

    def freq_max(self):
        """freq_max(self) -> double"""
        return _usrp_swig.db_base_freq_max(self)

    def set_freq(self, *args, **kwargs):
        """set_freq(self, double target_freq) -> freq_result_t"""
        return _usrp_swig.db_base_set_freq(self, *args, **kwargs)

    def set_gain(self, *args, **kwargs):
        """set_gain(self, float gain) -> bool"""
        return _usrp_swig.db_base_set_gain(self, *args, **kwargs)

    def is_quadrature(self):
        """is_quadrature(self) -> bool"""
        return _usrp_swig.db_base_is_quadrature(self)

    def i_and_q_swapped(self):
        """i_and_q_swapped(self) -> bool"""
        return _usrp_swig.db_base_i_and_q_swapped(self)

    def spectrum_inverted(self):
        """spectrum_inverted(self) -> bool"""
        return _usrp_swig.db_base_spectrum_inverted(self)

    def set_enable(self, *args, **kwargs):
        """set_enable(self, bool on) -> bool"""
        return _usrp_swig.db_base_set_enable(self, *args, **kwargs)

    def set_auto_tr(self, *args, **kwargs):
        """set_auto_tr(self, bool on) -> bool"""
        return _usrp_swig.db_base_set_auto_tr(self, *args, **kwargs)

    def select_rx_antenna(self, *args):
        """
        select_rx_antenna(self, int which_antenna) -> bool
        select_rx_antenna(self, string antenna) -> bool
        """
        return _usrp_swig.db_base_select_rx_antenna(self, *args)

    def set_bw(self, *args, **kwargs):
        """set_bw(self, float bw) -> bool"""
        return _usrp_swig.db_base_set_bw(self, *args, **kwargs)

db_base_swigregister = _usrp_swig.db_base_swigregister
db_base_swigregister(db_base)

class db_base_sptr(object):
    """Proxy of C++ boost::shared_ptr<(db_base)> class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    def __init__(self, *args): 
        """
        __init__(self) -> db_base_sptr
        __init__(self, db_base p) -> db_base_sptr
        """
        this = _usrp_swig.new_db_base_sptr(*args)
        try: self.this.append(this)
        except: self.this = this
    def __deref__(self):
        """__deref__(self) -> db_base"""
        return _usrp_swig.db_base_sptr___deref__(self)

    __swig_destroy__ = _usrp_swig.delete_db_base_sptr
    __del__ = lambda self : None;
    def dbid(self):
        """dbid(self) -> int"""
        return _usrp_swig.db_base_sptr_dbid(self)

    def name(self):
        """name(self) -> string"""
        return _usrp_swig.db_base_sptr_name(self)

    def side_and_name(self):
        """side_and_name(self) -> string"""
        return _usrp_swig.db_base_sptr_side_and_name(self)

    def which(self):
        """which(self) -> int"""
        return _usrp_swig.db_base_sptr_which(self)

    def bypass_adc_buffers(self, *args, **kwargs):
        """bypass_adc_buffers(self, bool bypass) -> bool"""
        return _usrp_swig.db_base_sptr_bypass_adc_buffers(self, *args, **kwargs)

    def set_atr_mask(self, *args, **kwargs):
        """set_atr_mask(self, int v) -> bool"""
        return _usrp_swig.db_base_sptr_set_atr_mask(self, *args, **kwargs)

    def set_atr_txval(self, *args, **kwargs):
        """set_atr_txval(self, int v) -> bool"""
        return _usrp_swig.db_base_sptr_set_atr_txval(self, *args, **kwargs)

    def set_atr_rxval(self, *args, **kwargs):
        """set_atr_rxval(self, int v) -> bool"""
        return _usrp_swig.db_base_sptr_set_atr_rxval(self, *args, **kwargs)

    def set_atr_tx_delay(self, *args, **kwargs):
        """set_atr_tx_delay(self, int v) -> bool"""
        return _usrp_swig.db_base_sptr_set_atr_tx_delay(self, *args, **kwargs)

    def set_atr_rx_delay(self, *args, **kwargs):
        """set_atr_rx_delay(self, int v) -> bool"""
        return _usrp_swig.db_base_sptr_set_atr_rx_delay(self, *args, **kwargs)

    def set_lo_offset(self, *args, **kwargs):
        """set_lo_offset(self, double offset) -> bool"""
        return _usrp_swig.db_base_sptr_set_lo_offset(self, *args, **kwargs)

    def lo_offset(self):
        """lo_offset(self) -> double"""
        return _usrp_swig.db_base_sptr_lo_offset(self)

    def gain_min(self):
        """gain_min(self) -> float"""
        return _usrp_swig.db_base_sptr_gain_min(self)

    def gain_max(self):
        """gain_max(self) -> float"""
        return _usrp_swig.db_base_sptr_gain_max(self)

    def gain_db_per_step(self):
        """gain_db_per_step(self) -> float"""
        return _usrp_swig.db_base_sptr_gain_db_per_step(self)

    def freq_min(self):
        """freq_min(self) -> double"""
        return _usrp_swig.db_base_sptr_freq_min(self)

    def freq_max(self):
        """freq_max(self) -> double"""
        return _usrp_swig.db_base_sptr_freq_max(self)

    def set_freq(self, *args, **kwargs):
        """set_freq(self, double target_freq) -> freq_result_t"""
        return _usrp_swig.db_base_sptr_set_freq(self, *args, **kwargs)

    def set_gain(self, *args, **kwargs):
        """set_gain(self, float gain) -> bool"""
        return _usrp_swig.db_base_sptr_set_gain(self, *args, **kwargs)

    def is_quadrature(self):
        """is_quadrature(self) -> bool"""
        return _usrp_swig.db_base_sptr_is_quadrature(self)

    def i_and_q_swapped(self):
        """i_and_q_swapped(self) -> bool"""
        return _usrp_swig.db_base_sptr_i_and_q_swapped(self)

    def spectrum_inverted(self):
        """spectrum_inverted(self) -> bool"""
        return _usrp_swig.db_base_sptr_spectrum_inverted(self)

    def set_enable(self, *args, **kwargs):
        """set_enable(self, bool on) -> bool"""
        return _usrp_swig.db_base_sptr_set_enable(self, *args, **kwargs)

    def set_auto_tr(self, *args, **kwargs):
        """set_auto_tr(self, bool on) -> bool"""
        return _usrp_swig.db_base_sptr_set_auto_tr(self, *args, **kwargs)

    def select_rx_antenna(self, *args):
        """
        select_rx_antenna(self, int which_antenna) -> bool
        select_rx_antenna(self, string antenna) -> bool
        """
        return _usrp_swig.db_base_sptr_select_rx_antenna(self, *args)

    def set_bw(self, *args, **kwargs):
        """set_bw(self, float bw) -> bool"""
        return _usrp_swig.db_base_sptr_set_bw(self, *args, **kwargs)

db_base_sptr_swigregister = _usrp_swig.db_base_sptr_swigregister
db_base_sptr_swigregister(db_base_sptr)

class db_base_sptr_vector(object):
    """Proxy of C++ std::vector<(db_base_sptr)> class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    def iterator(self):
        """iterator(self) -> SwigPyIterator"""
        return _usrp_swig.db_base_sptr_vector_iterator(self)

    def __iter__(self): return self.iterator()
    def __nonzero__(self):
        """__nonzero__(self) -> bool"""
        return _usrp_swig.db_base_sptr_vector___nonzero__(self)

    def __bool__(self):
        """__bool__(self) -> bool"""
        return _usrp_swig.db_base_sptr_vector___bool__(self)

    def __len__(self):
        """__len__(self) -> std::vector<(boost::shared_ptr<(db_base)>)>::size_type"""
        return _usrp_swig.db_base_sptr_vector___len__(self)

    def pop(self):
        """pop(self) -> std::vector<(boost::shared_ptr<(db_base)>)>::value_type"""
        return _usrp_swig.db_base_sptr_vector_pop(self)

    def __getslice__(self, *args, **kwargs):
        """
        __getslice__(self, std::vector<(boost::shared_ptr<(db_base)>)>::difference_type i, 
            std::vector<(boost::shared_ptr<(db_base)>)>::difference_type j) -> db_base_sptr_vector
        """
        return _usrp_swig.db_base_sptr_vector___getslice__(self, *args, **kwargs)

    def __setslice__(self, *args, **kwargs):
        """
        __setslice__(self, std::vector<(boost::shared_ptr<(db_base)>)>::difference_type i, 
            std::vector<(boost::shared_ptr<(db_base)>)>::difference_type j, 
            db_base_sptr_vector v)
        """
        return _usrp_swig.db_base_sptr_vector___setslice__(self, *args, **kwargs)

    def __delslice__(self, *args, **kwargs):
        """
        __delslice__(self, std::vector<(boost::shared_ptr<(db_base)>)>::difference_type i, 
            std::vector<(boost::shared_ptr<(db_base)>)>::difference_type j)
        """
        return _usrp_swig.db_base_sptr_vector___delslice__(self, *args, **kwargs)

    def __delitem__(self, *args):
        """
        __delitem__(self, std::vector<(boost::shared_ptr<(db_base)>)>::difference_type i)
        __delitem__(self, PySliceObject slice)
        """
        return _usrp_swig.db_base_sptr_vector___delitem__(self, *args)

    def __getitem__(self, *args):
        """
        __getitem__(self, PySliceObject slice) -> db_base_sptr_vector
        __getitem__(self, std::vector<(boost::shared_ptr<(db_base)>)>::difference_type i) -> std::vector<(boost::shared_ptr<(db_base)>)>::value_type
        """
        return _usrp_swig.db_base_sptr_vector___getitem__(self, *args)

    def __setitem__(self, *args):
        """
        __setitem__(self, PySliceObject slice, db_base_sptr_vector v)
        __setitem__(self, std::vector<(boost::shared_ptr<(db_base)>)>::difference_type i, 
            std::vector<(boost::shared_ptr<(db_base)>)>::value_type x)
        """
        return _usrp_swig.db_base_sptr_vector___setitem__(self, *args)

    def append(self, *args, **kwargs):
        """append(self, std::vector<(boost::shared_ptr<(db_base)>)>::value_type x)"""
        return _usrp_swig.db_base_sptr_vector_append(self, *args, **kwargs)

    def empty(self):
        """empty(self) -> bool"""
        return _usrp_swig.db_base_sptr_vector_empty(self)

    def size(self):
        """size(self) -> std::vector<(boost::shared_ptr<(db_base)>)>::size_type"""
        return _usrp_swig.db_base_sptr_vector_size(self)

    def clear(self):
        """clear(self)"""
        return _usrp_swig.db_base_sptr_vector_clear(self)

    def swap(self, *args, **kwargs):
        """swap(self, db_base_sptr_vector v)"""
        return _usrp_swig.db_base_sptr_vector_swap(self, *args, **kwargs)

    def get_allocator(self):
        """get_allocator(self) -> std::vector<(boost::shared_ptr<(db_base)>)>::allocator_type"""
        return _usrp_swig.db_base_sptr_vector_get_allocator(self)

    def begin(self):
        """begin(self) -> std::vector<(boost::shared_ptr<(db_base)>)>::const_iterator"""
        return _usrp_swig.db_base_sptr_vector_begin(self)

    def end(self):
        """end(self) -> std::vector<(boost::shared_ptr<(db_base)>)>::const_iterator"""
        return _usrp_swig.db_base_sptr_vector_end(self)

    def rbegin(self):
        """rbegin(self) -> std::vector<(boost::shared_ptr<(db_base)>)>::const_reverse_iterator"""
        return _usrp_swig.db_base_sptr_vector_rbegin(self)

    def rend(self):
        """rend(self) -> std::vector<(boost::shared_ptr<(db_base)>)>::const_reverse_iterator"""
        return _usrp_swig.db_base_sptr_vector_rend(self)

    def pop_back(self):
        """pop_back(self)"""
        return _usrp_swig.db_base_sptr_vector_pop_back(self)

    def erase(self, *args):
        """
        erase(self, std::vector<(boost::shared_ptr<(db_base)>)>::iterator pos) -> std::vector<(boost::shared_ptr<(db_base)>)>::iterator
        erase(self, std::vector<(boost::shared_ptr<(db_base)>)>::iterator first, 
            std::vector<(boost::shared_ptr<(db_base)>)>::iterator last) -> std::vector<(boost::shared_ptr<(db_base)>)>::iterator
        """
        return _usrp_swig.db_base_sptr_vector_erase(self, *args)

    def __init__(self, *args): 
        """
        __init__(self) -> db_base_sptr_vector
        __init__(self, db_base_sptr_vector arg0) -> db_base_sptr_vector
        __init__(self, std::vector<(boost::shared_ptr<(db_base)>)>::size_type size) -> db_base_sptr_vector
        __init__(self, std::vector<(boost::shared_ptr<(db_base)>)>::size_type size, 
            std::vector<(boost::shared_ptr<(db_base)>)>::value_type value) -> db_base_sptr_vector
        """
        this = _usrp_swig.new_db_base_sptr_vector(*args)
        try: self.this.append(this)
        except: self.this = this
    def push_back(self, *args, **kwargs):
        """push_back(self, std::vector<(boost::shared_ptr<(db_base)>)>::value_type x)"""
        return _usrp_swig.db_base_sptr_vector_push_back(self, *args, **kwargs)

    def front(self):
        """front(self) -> std::vector<(boost::shared_ptr<(db_base)>)>::value_type"""
        return _usrp_swig.db_base_sptr_vector_front(self)

    def back(self):
        """back(self) -> std::vector<(boost::shared_ptr<(db_base)>)>::value_type"""
        return _usrp_swig.db_base_sptr_vector_back(self)

    def assign(self, *args, **kwargs):
        """
        assign(self, std::vector<(boost::shared_ptr<(db_base)>)>::size_type n, 
            std::vector<(boost::shared_ptr<(db_base)>)>::value_type x)
        """
        return _usrp_swig.db_base_sptr_vector_assign(self, *args, **kwargs)

    def resize(self, *args):
        """
        resize(self, std::vector<(boost::shared_ptr<(db_base)>)>::size_type new_size)
        resize(self, std::vector<(boost::shared_ptr<(db_base)>)>::size_type new_size, 
            std::vector<(boost::shared_ptr<(db_base)>)>::value_type x)
        """
        return _usrp_swig.db_base_sptr_vector_resize(self, *args)

    def insert(self, *args):
        """
        insert(self, std::vector<(boost::shared_ptr<(db_base)>)>::iterator pos, 
            std::vector<(boost::shared_ptr<(db_base)>)>::value_type x) -> std::vector<(boost::shared_ptr<(db_base)>)>::iterator
        insert(self, std::vector<(boost::shared_ptr<(db_base)>)>::iterator pos, 
            std::vector<(boost::shared_ptr<(db_base)>)>::size_type n, 
            std::vector<(boost::shared_ptr<(db_base)>)>::value_type x)
        """
        return _usrp_swig.db_base_sptr_vector_insert(self, *args)

    def reserve(self, *args, **kwargs):
        """reserve(self, std::vector<(boost::shared_ptr<(db_base)>)>::size_type n)"""
        return _usrp_swig.db_base_sptr_vector_reserve(self, *args, **kwargs)

    def capacity(self):
        """capacity(self) -> std::vector<(boost::shared_ptr<(db_base)>)>::size_type"""
        return _usrp_swig.db_base_sptr_vector_capacity(self)

    __swig_destroy__ = _usrp_swig.delete_db_base_sptr_vector
    __del__ = lambda self : None;
db_base_sptr_vector_swigregister = _usrp_swig.db_base_sptr_vector_swigregister
db_base_sptr_vector_swigregister(db_base_sptr_vector)

class db_base_sptr_vector_vector(object):
    """Proxy of C++ std::vector<(std::vector<(db_base_sptr)>)> class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    def iterator(self):
        """iterator(self) -> SwigPyIterator"""
        return _usrp_swig.db_base_sptr_vector_vector_iterator(self)

    def __iter__(self): return self.iterator()
    def __nonzero__(self):
        """__nonzero__(self) -> bool"""
        return _usrp_swig.db_base_sptr_vector_vector___nonzero__(self)

    def __bool__(self):
        """__bool__(self) -> bool"""
        return _usrp_swig.db_base_sptr_vector_vector___bool__(self)

    def __len__(self):
        """__len__(self) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::size_type"""
        return _usrp_swig.db_base_sptr_vector_vector___len__(self)

    def pop(self):
        """pop(self) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::value_type"""
        return _usrp_swig.db_base_sptr_vector_vector_pop(self)

    def __getslice__(self, *args, **kwargs):
        """
        __getslice__(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::difference_type i, 
            std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::difference_type j) -> db_base_sptr_vector_vector
        """
        return _usrp_swig.db_base_sptr_vector_vector___getslice__(self, *args, **kwargs)

    def __setslice__(self, *args, **kwargs):
        """
        __setslice__(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::difference_type i, 
            std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::difference_type j, 
            db_base_sptr_vector_vector v)
        """
        return _usrp_swig.db_base_sptr_vector_vector___setslice__(self, *args, **kwargs)

    def __delslice__(self, *args, **kwargs):
        """
        __delslice__(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::difference_type i, 
            std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::difference_type j)
        """
        return _usrp_swig.db_base_sptr_vector_vector___delslice__(self, *args, **kwargs)

    def __delitem__(self, *args):
        """
        __delitem__(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::difference_type i)
        __delitem__(self, PySliceObject slice)
        """
        return _usrp_swig.db_base_sptr_vector_vector___delitem__(self, *args)

    def __getitem__(self, *args):
        """
        __getitem__(self, PySliceObject slice) -> db_base_sptr_vector_vector
        __getitem__(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::difference_type i) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::value_type
        """
        return _usrp_swig.db_base_sptr_vector_vector___getitem__(self, *args)

    def __setitem__(self, *args):
        """
        __setitem__(self, PySliceObject slice, db_base_sptr_vector_vector v)
        __setitem__(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::difference_type i, 
            std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::value_type x)
        """
        return _usrp_swig.db_base_sptr_vector_vector___setitem__(self, *args)

    def append(self, *args, **kwargs):
        """append(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::value_type x)"""
        return _usrp_swig.db_base_sptr_vector_vector_append(self, *args, **kwargs)

    def empty(self):
        """empty(self) -> bool"""
        return _usrp_swig.db_base_sptr_vector_vector_empty(self)

    def size(self):
        """size(self) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::size_type"""
        return _usrp_swig.db_base_sptr_vector_vector_size(self)

    def clear(self):
        """clear(self)"""
        return _usrp_swig.db_base_sptr_vector_vector_clear(self)

    def swap(self, *args, **kwargs):
        """swap(self, db_base_sptr_vector_vector v)"""
        return _usrp_swig.db_base_sptr_vector_vector_swap(self, *args, **kwargs)

    def get_allocator(self):
        """get_allocator(self) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::allocator_type"""
        return _usrp_swig.db_base_sptr_vector_vector_get_allocator(self)

    def begin(self):
        """begin(self) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::const_iterator"""
        return _usrp_swig.db_base_sptr_vector_vector_begin(self)

    def end(self):
        """end(self) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::const_iterator"""
        return _usrp_swig.db_base_sptr_vector_vector_end(self)

    def rbegin(self):
        """rbegin(self) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::const_reverse_iterator"""
        return _usrp_swig.db_base_sptr_vector_vector_rbegin(self)

    def rend(self):
        """rend(self) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::const_reverse_iterator"""
        return _usrp_swig.db_base_sptr_vector_vector_rend(self)

    def pop_back(self):
        """pop_back(self)"""
        return _usrp_swig.db_base_sptr_vector_vector_pop_back(self)

    def erase(self, *args):
        """
        erase(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::iterator pos) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::iterator
        erase(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::iterator first, 
            std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::iterator last) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::iterator
        """
        return _usrp_swig.db_base_sptr_vector_vector_erase(self, *args)

    def __init__(self, *args): 
        """
        __init__(self) -> db_base_sptr_vector_vector
        __init__(self, db_base_sptr_vector_vector arg0) -> db_base_sptr_vector_vector
        __init__(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::size_type size) -> db_base_sptr_vector_vector
        __init__(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::size_type size, 
            std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::value_type value) -> db_base_sptr_vector_vector
        """
        this = _usrp_swig.new_db_base_sptr_vector_vector(*args)
        try: self.this.append(this)
        except: self.this = this
    def push_back(self, *args, **kwargs):
        """push_back(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::value_type x)"""
        return _usrp_swig.db_base_sptr_vector_vector_push_back(self, *args, **kwargs)

    def front(self):
        """front(self) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::value_type"""
        return _usrp_swig.db_base_sptr_vector_vector_front(self)

    def back(self):
        """back(self) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::value_type"""
        return _usrp_swig.db_base_sptr_vector_vector_back(self)

    def assign(self, *args, **kwargs):
        """
        assign(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::size_type n, 
            std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::value_type x)
        """
        return _usrp_swig.db_base_sptr_vector_vector_assign(self, *args, **kwargs)

    def resize(self, *args):
        """
        resize(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::size_type new_size)
        resize(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::size_type new_size, 
            std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::value_type x)
        """
        return _usrp_swig.db_base_sptr_vector_vector_resize(self, *args)

    def insert(self, *args):
        """
        insert(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::iterator pos, 
            std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::value_type x) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::iterator
        insert(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::iterator pos, 
            std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::size_type n, 
            std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::value_type x)
        """
        return _usrp_swig.db_base_sptr_vector_vector_insert(self, *args)

    def reserve(self, *args, **kwargs):
        """reserve(self, std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::size_type n)"""
        return _usrp_swig.db_base_sptr_vector_vector_reserve(self, *args, **kwargs)

    def capacity(self):
        """capacity(self) -> std::vector<(std::vector<(boost::shared_ptr<(db_base)>)>)>::size_type"""
        return _usrp_swig.db_base_sptr_vector_vector_capacity(self)

    __swig_destroy__ = _usrp_swig.delete_db_base_sptr_vector_vector
    __del__ = lambda self : None;
db_base_sptr_vector_vector_swigregister = _usrp_swig.db_base_sptr_vector_vector_swigregister
db_base_sptr_vector_vector_swigregister(db_base_sptr_vector_vector)

db_base_sptr.__repr__ = lambda self: "<db_base::%s>" % (self.name(),)
db_base_sptr.freq_range = lambda self: (self.freq_min(), self.freq_max(), 1)
db_base_sptr.gain_range = lambda self: (self.gain_min(), self.gain_max(), self.gain_db_per_step())


FR_TX_SAMPLE_RATE_DIV = _usrp_swig.FR_TX_SAMPLE_RATE_DIV
FR_RX_SAMPLE_RATE_DIV = _usrp_swig.FR_RX_SAMPLE_RATE_DIV
FR_MASTER_CTRL = _usrp_swig.FR_MASTER_CTRL
bmFR_MC_ENABLE_TX = _usrp_swig.bmFR_MC_ENABLE_TX
bmFR_MC_ENABLE_RX = _usrp_swig.bmFR_MC_ENABLE_RX
bmFR_MC_RESET_TX = _usrp_swig.bmFR_MC_RESET_TX
bmFR_MC_RESET_RX = _usrp_swig.bmFR_MC_RESET_RX
FR_OE_0 = _usrp_swig.FR_OE_0
FR_OE_1 = _usrp_swig.FR_OE_1
FR_OE_2 = _usrp_swig.FR_OE_2
FR_OE_3 = _usrp_swig.FR_OE_3
FR_IO_0 = _usrp_swig.FR_IO_0
FR_IO_1 = _usrp_swig.FR_IO_1
FR_IO_2 = _usrp_swig.FR_IO_2
FR_IO_3 = _usrp_swig.FR_IO_3
FR_MODE = _usrp_swig.FR_MODE
bmFR_MODE_NORMAL = _usrp_swig.bmFR_MODE_NORMAL
bmFR_MODE_LOOPBACK = _usrp_swig.bmFR_MODE_LOOPBACK
bmFR_MODE_RX_COUNTING = _usrp_swig.bmFR_MODE_RX_COUNTING
bmFR_MODE_RX_COUNTING_32BIT = _usrp_swig.bmFR_MODE_RX_COUNTING_32BIT
FR_DEBUG_EN = _usrp_swig.FR_DEBUG_EN
bmFR_DEBUG_EN_TX_A = _usrp_swig.bmFR_DEBUG_EN_TX_A
bmFR_DEBUG_EN_RX_A = _usrp_swig.bmFR_DEBUG_EN_RX_A
bmFR_DEBUG_EN_TX_B = _usrp_swig.bmFR_DEBUG_EN_TX_B
bmFR_DEBUG_EN_RX_B = _usrp_swig.bmFR_DEBUG_EN_RX_B
FR_DC_OFFSET_CL_EN = _usrp_swig.FR_DC_OFFSET_CL_EN
FR_ADC_OFFSET_0 = _usrp_swig.FR_ADC_OFFSET_0
FR_ADC_OFFSET_1 = _usrp_swig.FR_ADC_OFFSET_1
FR_ADC_OFFSET_2 = _usrp_swig.FR_ADC_OFFSET_2
FR_ADC_OFFSET_3 = _usrp_swig.FR_ADC_OFFSET_3
FR_ATR_MASK_0 = _usrp_swig.FR_ATR_MASK_0
FR_ATR_TXVAL_0 = _usrp_swig.FR_ATR_TXVAL_0
FR_ATR_RXVAL_0 = _usrp_swig.FR_ATR_RXVAL_0
FR_ATR_MASK_1 = _usrp_swig.FR_ATR_MASK_1
FR_ATR_TXVAL_1 = _usrp_swig.FR_ATR_TXVAL_1
FR_ATR_RXVAL_1 = _usrp_swig.FR_ATR_RXVAL_1
FR_ATR_MASK_2 = _usrp_swig.FR_ATR_MASK_2
FR_ATR_TXVAL_2 = _usrp_swig.FR_ATR_TXVAL_2
FR_ATR_RXVAL_2 = _usrp_swig.FR_ATR_RXVAL_2
FR_ATR_MASK_3 = _usrp_swig.FR_ATR_MASK_3
FR_ATR_TXVAL_3 = _usrp_swig.FR_ATR_TXVAL_3
FR_ATR_RXVAL_3 = _usrp_swig.FR_ATR_RXVAL_3
FR_ATR_TX_DELAY = _usrp_swig.FR_ATR_TX_DELAY
FR_ATR_RX_DELAY = _usrp_swig.FR_ATR_RX_DELAY
FR_INTERP_RATE = _usrp_swig.FR_INTERP_RATE
FR_DECIM_RATE = _usrp_swig.FR_DECIM_RATE
FR_RX_FREQ_0 = _usrp_swig.FR_RX_FREQ_0
FR_RX_FREQ_1 = _usrp_swig.FR_RX_FREQ_1
FR_RX_FREQ_2 = _usrp_swig.FR_RX_FREQ_2
FR_RX_FREQ_3 = _usrp_swig.FR_RX_FREQ_3
FR_RX_MUX = _usrp_swig.FR_RX_MUX
FR_TX_MUX = _usrp_swig.FR_TX_MUX
FR_TX_A_REFCLK = _usrp_swig.FR_TX_A_REFCLK
FR_RX_A_REFCLK = _usrp_swig.FR_RX_A_REFCLK
FR_TX_B_REFCLK = _usrp_swig.FR_TX_B_REFCLK
FR_RX_B_REFCLK = _usrp_swig.FR_RX_B_REFCLK
bmFR_REFCLK_EN = _usrp_swig.bmFR_REFCLK_EN
bmFR_REFCLK_DIVISOR_MASK = _usrp_swig.bmFR_REFCLK_DIVISOR_MASK
FR_RX_PHASE_0 = _usrp_swig.FR_RX_PHASE_0
FR_RX_PHASE_1 = _usrp_swig.FR_RX_PHASE_1
FR_RX_PHASE_2 = _usrp_swig.FR_RX_PHASE_2
FR_RX_PHASE_3 = _usrp_swig.FR_RX_PHASE_3
FR_TX_FORMAT = _usrp_swig.FR_TX_FORMAT
bmFR_TX_FORMAT_16_IQ = _usrp_swig.bmFR_TX_FORMAT_16_IQ
FR_RX_FORMAT = _usrp_swig.FR_RX_FORMAT
bmFR_RX_FORMAT_SHIFT_MASK = _usrp_swig.bmFR_RX_FORMAT_SHIFT_MASK
bmFR_RX_FORMAT_SHIFT_SHIFT = _usrp_swig.bmFR_RX_FORMAT_SHIFT_SHIFT
bmFR_RX_FORMAT_WIDTH_MASK = _usrp_swig.bmFR_RX_FORMAT_WIDTH_MASK
bmFR_RX_FORMAT_WIDTH_SHIFT = _usrp_swig.bmFR_RX_FORMAT_WIDTH_SHIFT
bmFR_RX_FORMAT_WANT_Q = _usrp_swig.bmFR_RX_FORMAT_WANT_Q
bmFR_RX_FORMAT_BYPASS_HB = _usrp_swig.bmFR_RX_FORMAT_BYPASS_HB
FR_USER_0 = _usrp_swig.FR_USER_0
FR_USER_1 = _usrp_swig.FR_USER_1
FR_USER_2 = _usrp_swig.FR_USER_2
FR_USER_3 = _usrp_swig.FR_USER_3
FR_USER_4 = _usrp_swig.FR_USER_4
FR_USER_5 = _usrp_swig.FR_USER_5
FR_USER_6 = _usrp_swig.FR_USER_6
FR_USER_7 = _usrp_swig.FR_USER_7
FR_USER_8 = _usrp_swig.FR_USER_8
FR_USER_9 = _usrp_swig.FR_USER_9
FR_USER_10 = _usrp_swig.FR_USER_10
FR_USER_11 = _usrp_swig.FR_USER_11
FR_USER_12 = _usrp_swig.FR_USER_12
FR_USER_13 = _usrp_swig.FR_USER_13
FR_USER_14 = _usrp_swig.FR_USER_14
FR_USER_15 = _usrp_swig.FR_USER_15
FR_USER_16 = _usrp_swig.FR_USER_16
FR_USER_17 = _usrp_swig.FR_USER_17
FR_USER_18 = _usrp_swig.FR_USER_18
FR_USER_19 = _usrp_swig.FR_USER_19
FR_USER_20 = _usrp_swig.FR_USER_20
FR_USER_21 = _usrp_swig.FR_USER_21
FR_USER_22 = _usrp_swig.FR_USER_22
FR_USER_23 = _usrp_swig.FR_USER_23
FR_USER_24 = _usrp_swig.FR_USER_24
FR_USER_25 = _usrp_swig.FR_USER_25
FR_USER_26 = _usrp_swig.FR_USER_26
FR_USER_27 = _usrp_swig.FR_USER_27
FR_USER_28 = _usrp_swig.FR_USER_28
FR_USER_29 = _usrp_swig.FR_USER_29
FR_USER_30 = _usrp_swig.FR_USER_30
FR_USER_31 = _usrp_swig.FR_USER_31
FR_RX_MASTER_SLAVE = _usrp_swig.FR_RX_MASTER_SLAVE
bitnoFR_RX_SYNC = _usrp_swig.bitnoFR_RX_SYNC
bitnoFR_RX_SYNC_MASTER = _usrp_swig.bitnoFR_RX_SYNC_MASTER
bitnoFR_RX_SYNC_SLAVE = _usrp_swig.bitnoFR_RX_SYNC_SLAVE
bmFR_RX_SYNC = _usrp_swig.bmFR_RX_SYNC
bmFR_RX_SYNC_MASTER = _usrp_swig.bmFR_RX_SYNC_MASTER
bmFR_RX_SYNC_SLAVE = _usrp_swig.bmFR_RX_SYNC_SLAVE
bitnoFR_RX_SYNC_INPUT_IOPIN = _usrp_swig.bitnoFR_RX_SYNC_INPUT_IOPIN
bmFR_RX_SYNC_INPUT_IOPIN = _usrp_swig.bmFR_RX_SYNC_INPUT_IOPIN
bitnoFR_RX_SYNC_OUTPUT_IOPIN = _usrp_swig.bitnoFR_RX_SYNC_OUTPUT_IOPIN
bmFR_RX_SYNC_OUTPUT_IOPIN = _usrp_swig.bmFR_RX_SYNC_OUTPUT_IOPIN
FR_RB_IO_RX_A_IO_TX_A = _usrp_swig.FR_RB_IO_RX_A_IO_TX_A
FR_RB_IO_RX_B_IO_TX_B = _usrp_swig.FR_RB_IO_RX_B_IO_TX_B
FR_RB_CAPS = _usrp_swig.FR_RB_CAPS
bmFR_RB_CAPS_NDDC_MASK = _usrp_swig.bmFR_RB_CAPS_NDDC_MASK
bmFR_RB_CAPS_NDDC_SHIFT = _usrp_swig.bmFR_RB_CAPS_NDDC_SHIFT
bmFR_RB_CAPS_RX_HAS_HALFBAND = _usrp_swig.bmFR_RB_CAPS_RX_HAS_HALFBAND
bmFR_RB_CAPS_NDUC_MASK = _usrp_swig.bmFR_RB_CAPS_NDUC_MASK
bmFR_RB_CAPS_NDUC_SHIFT = _usrp_swig.bmFR_RB_CAPS_NDUC_SHIFT
bmFR_RB_CAPS_TX_HAS_HALFBAND = _usrp_swig.bmFR_RB_CAPS_TX_HAS_HALFBAND
SPI_FMT_xSB_MASK = _usrp_swig.SPI_FMT_xSB_MASK
SPI_FMT_LSB = _usrp_swig.SPI_FMT_LSB
SPI_FMT_MSB = _usrp_swig.SPI_FMT_MSB
SPI_FMT_HDR_MASK = _usrp_swig.SPI_FMT_HDR_MASK
SPI_FMT_HDR_0 = _usrp_swig.SPI_FMT_HDR_0
SPI_FMT_HDR_1 = _usrp_swig.SPI_FMT_HDR_1
SPI_FMT_HDR_2 = _usrp_swig.SPI_FMT_HDR_2
SPI_ENABLE_FPGA = _usrp_swig.SPI_ENABLE_FPGA
SPI_ENABLE_CODEC_A = _usrp_swig.SPI_ENABLE_CODEC_A
SPI_ENABLE_CODEC_B = _usrp_swig.SPI_ENABLE_CODEC_B
SPI_ENABLE_reserved = _usrp_swig.SPI_ENABLE_reserved
SPI_ENABLE_TX_A = _usrp_swig.SPI_ENABLE_TX_A
SPI_ENABLE_RX_A = _usrp_swig.SPI_ENABLE_RX_A
SPI_ENABLE_TX_B = _usrp_swig.SPI_ENABLE_TX_B
SPI_ENABLE_RX_B = _usrp_swig.SPI_ENABLE_RX_B
USRP_DBID_BASIC_TX = _usrp_swig.USRP_DBID_BASIC_TX
USRP_DBID_BASIC_RX = _usrp_swig.USRP_DBID_BASIC_RX
USRP_DBID_DBS_RX = _usrp_swig.USRP_DBID_DBS_RX
USRP_DBID_TV_RX = _usrp_swig.USRP_DBID_TV_RX
USRP_DBID_FLEX_400_RX = _usrp_swig.USRP_DBID_FLEX_400_RX
USRP_DBID_FLEX_900_RX = _usrp_swig.USRP_DBID_FLEX_900_RX
USRP_DBID_FLEX_1200_RX = _usrp_swig.USRP_DBID_FLEX_1200_RX
USRP_DBID_FLEX_2400_RX = _usrp_swig.USRP_DBID_FLEX_2400_RX
USRP_DBID_FLEX_400_TX = _usrp_swig.USRP_DBID_FLEX_400_TX
USRP_DBID_FLEX_900_TX = _usrp_swig.USRP_DBID_FLEX_900_TX
USRP_DBID_FLEX_1200_TX = _usrp_swig.USRP_DBID_FLEX_1200_TX
USRP_DBID_FLEX_2400_TX = _usrp_swig.USRP_DBID_FLEX_2400_TX
USRP_DBID_TV_RX_REV_2 = _usrp_swig.USRP_DBID_TV_RX_REV_2
USRP_DBID_DBS_RX_CLKMOD = _usrp_swig.USRP_DBID_DBS_RX_CLKMOD
USRP_DBID_LF_TX = _usrp_swig.USRP_DBID_LF_TX
USRP_DBID_LF_RX = _usrp_swig.USRP_DBID_LF_RX
USRP_DBID_FLEX_400_RX_MIMO_A = _usrp_swig.USRP_DBID_FLEX_400_RX_MIMO_A
USRP_DBID_FLEX_900_RX_MIMO_A = _usrp_swig.USRP_DBID_FLEX_900_RX_MIMO_A
USRP_DBID_FLEX_1200_RX_MIMO_A = _usrp_swig.USRP_DBID_FLEX_1200_RX_MIMO_A
USRP_DBID_FLEX_2400_RX_MIMO_A = _usrp_swig.USRP_DBID_FLEX_2400_RX_MIMO_A
USRP_DBID_FLEX_400_TX_MIMO_A = _usrp_swig.USRP_DBID_FLEX_400_TX_MIMO_A
USRP_DBID_FLEX_900_TX_MIMO_A = _usrp_swig.USRP_DBID_FLEX_900_TX_MIMO_A
USRP_DBID_FLEX_1200_TX_MIMO_A = _usrp_swig.USRP_DBID_FLEX_1200_TX_MIMO_A
USRP_DBID_FLEX_2400_TX_MIMO_A = _usrp_swig.USRP_DBID_FLEX_2400_TX_MIMO_A
USRP_DBID_FLEX_400_RX_MIMO_B = _usrp_swig.USRP_DBID_FLEX_400_RX_MIMO_B
USRP_DBID_FLEX_900_RX_MIMO_B = _usrp_swig.USRP_DBID_FLEX_900_RX_MIMO_B
USRP_DBID_FLEX_1200_RX_MIMO_B = _usrp_swig.USRP_DBID_FLEX_1200_RX_MIMO_B
USRP_DBID_FLEX_2400_RX_MIMO_B = _usrp_swig.USRP_DBID_FLEX_2400_RX_MIMO_B
USRP_DBID_FLEX_400_TX_MIMO_B = _usrp_swig.USRP_DBID_FLEX_400_TX_MIMO_B
USRP_DBID_FLEX_900_TX_MIMO_B = _usrp_swig.USRP_DBID_FLEX_900_TX_MIMO_B
USRP_DBID_FLEX_1200_TX_MIMO_B = _usrp_swig.USRP_DBID_FLEX_1200_TX_MIMO_B
USRP_DBID_FLEX_2400_TX_MIMO_B = _usrp_swig.USRP_DBID_FLEX_2400_TX_MIMO_B
USRP_DBID_FLEX_1800_RX = _usrp_swig.USRP_DBID_FLEX_1800_RX
USRP_DBID_FLEX_1800_TX = _usrp_swig.USRP_DBID_FLEX_1800_TX
USRP_DBID_FLEX_1800_RX_MIMO_A = _usrp_swig.USRP_DBID_FLEX_1800_RX_MIMO_A
USRP_DBID_FLEX_1800_TX_MIMO_A = _usrp_swig.USRP_DBID_FLEX_1800_TX_MIMO_A
USRP_DBID_FLEX_1800_RX_MIMO_B = _usrp_swig.USRP_DBID_FLEX_1800_RX_MIMO_B
USRP_DBID_FLEX_1800_TX_MIMO_B = _usrp_swig.USRP_DBID_FLEX_1800_TX_MIMO_B
USRP_DBID_TV_RX_REV_3 = _usrp_swig.USRP_DBID_TV_RX_REV_3
USRP_DBID_DTT754 = _usrp_swig.USRP_DBID_DTT754
USRP_DBID_DTT768 = _usrp_swig.USRP_DBID_DTT768
USRP_DBID_WBX_LO_TX = _usrp_swig.USRP_DBID_WBX_LO_TX
USRP_DBID_WBX_LO_RX = _usrp_swig.USRP_DBID_WBX_LO_RX
USRP_DBID_XCVR2450_TX = _usrp_swig.USRP_DBID_XCVR2450_TX
USRP_DBID_XCVR2450_RX = _usrp_swig.USRP_DBID_XCVR2450_RX
USRP_DBID_EXPERIMENTAL_TX = _usrp_swig.USRP_DBID_EXPERIMENTAL_TX
USRP_DBID_EXPERIMENTAL_RX = _usrp_swig.USRP_DBID_EXPERIMENTAL_RX
FPGA_MODE_NORMAL = _usrp_swig.FPGA_MODE_NORMAL
FPGA_MODE_LOOPBACK = _usrp_swig.FPGA_MODE_LOOPBACK
FPGA_MODE_COUNTING = _usrp_swig.FPGA_MODE_COUNTING
class usrp_base(object):
    """Proxy of C++ usrp_base class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    def __init__(self, *args, **kwargs): raise AttributeError("No constructor defined")
    __repr__ = _swig_repr
    def db(self, *args):
        """
        db(self) -> db_base_sptr_vector_vector
        db(self, int which_side) -> db_base_sptr_vector
        db(self, int which_side, int which_dev) -> db_base_sptr
        """
        return _usrp_swig.usrp_base_db(self, *args)

    def _real_selected_subdev(self, *args, **kwargs):
        """_real_selected_subdev(self, usrp_subdev_spec ss) -> db_base_sptr"""
        return _usrp_swig.usrp_base__real_selected_subdev(self, *args, **kwargs)

    def fpga_master_clock_freq(self):
        """fpga_master_clock_freq(self) -> long"""
        return _usrp_swig.usrp_base_fpga_master_clock_freq(self)

    def set_fpga_master_clock_freq(self, *args, **kwargs):
        """set_fpga_master_clock_freq(self, long master_clock)"""
        return _usrp_swig.usrp_base_set_fpga_master_clock_freq(self, *args, **kwargs)

    def set_verbose(self, *args, **kwargs):
        """set_verbose(self, bool on)"""
        return _usrp_swig.usrp_base_set_verbose(self, *args, **kwargs)

    READ_FAILED = _usrp_swig.usrp_base_READ_FAILED
    def write_eeprom(self, *args, **kwargs):
        """write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) -> bool"""
        return _usrp_swig.usrp_base_write_eeprom(self, *args, **kwargs)

    def read_eeprom(self, *args, **kwargs):
        """read_eeprom(self, int i2c_addr, int eeprom_offset, int len) -> string"""
        return _usrp_swig.usrp_base_read_eeprom(self, *args, **kwargs)

    def write_i2c(self, *args, **kwargs):
        """write_i2c(self, int i2c_addr, string buf) -> bool"""
        return _usrp_swig.usrp_base_write_i2c(self, *args, **kwargs)

    def read_i2c(self, *args, **kwargs):
        """read_i2c(self, int i2c_addr, int len) -> string"""
        return _usrp_swig.usrp_base_read_i2c(self, *args, **kwargs)

    def set_adc_offset(self, *args, **kwargs):
        """set_adc_offset(self, int which_adc, int offset) -> bool"""
        return _usrp_swig.usrp_base_set_adc_offset(self, *args, **kwargs)

    def set_dac_offset(self, *args, **kwargs):
        """set_dac_offset(self, int which_dac, int offset, int offset_pin) -> bool"""
        return _usrp_swig.usrp_base_set_dac_offset(self, *args, **kwargs)

    def set_adc_buffer_bypass(self, *args, **kwargs):
        """set_adc_buffer_bypass(self, int which_adc, bool bypass) -> bool"""
        return _usrp_swig.usrp_base_set_adc_buffer_bypass(self, *args, **kwargs)

    def set_dc_offset_cl_enable(self, *args, **kwargs):
        """set_dc_offset_cl_enable(self, int bits, int mask) -> bool"""
        return _usrp_swig.usrp_base_set_dc_offset_cl_enable(self, *args, **kwargs)

    def serial_number(self):
        """serial_number(self) -> string"""
        return _usrp_swig.usrp_base_serial_number(self)

    def daughterboard_id(self, *args, **kwargs):
        """daughterboard_id(self, int which_side) -> int"""
        return _usrp_swig.usrp_base_daughterboard_id(self, *args, **kwargs)

    def write_atr_tx_delay(self, *args, **kwargs):
        """write_atr_tx_delay(self, int value) -> bool"""
        return _usrp_swig.usrp_base_write_atr_tx_delay(self, *args, **kwargs)

    def write_atr_rx_delay(self, *args, **kwargs):
        """write_atr_rx_delay(self, int value) -> bool"""
        return _usrp_swig.usrp_base_write_atr_rx_delay(self, *args, **kwargs)

    def set_pga(self, *args, **kwargs):
        """set_pga(self, int which_amp, double gain_in_db) -> bool"""
        return _usrp_swig.usrp_base_set_pga(self, *args, **kwargs)

    def pga(self, *args, **kwargs):
        """pga(self, int which_amp) -> double"""
        return _usrp_swig.usrp_base_pga(self, *args, **kwargs)

    def pga_min(self):
        """pga_min(self) -> double"""
        return _usrp_swig.usrp_base_pga_min(self)

    def pga_max(self):
        """pga_max(self) -> double"""
        return _usrp_swig.usrp_base_pga_max(self)

    def pga_db_per_step(self):
        """pga_db_per_step(self) -> double"""
        return _usrp_swig.usrp_base_pga_db_per_step(self)

    def _write_oe(self, *args, **kwargs):
        """_write_oe(self, int which_side, int value, int mask) -> bool"""
        return _usrp_swig.usrp_base__write_oe(self, *args, **kwargs)

    def write_io(self, *args, **kwargs):
        """write_io(self, int which_side, int value, int mask) -> bool"""
        return _usrp_swig.usrp_base_write_io(self, *args, **kwargs)

    def read_io(self, *args, **kwargs):
        """read_io(self, int which_side) -> int"""
        return _usrp_swig.usrp_base_read_io(self, *args, **kwargs)

    def write_atr_mask(self, *args, **kwargs):
        """write_atr_mask(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_base_write_atr_mask(self, *args, **kwargs)

    def write_atr_txval(self, *args, **kwargs):
        """write_atr_txval(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_base_write_atr_txval(self, *args, **kwargs)

    def write_atr_rxval(self, *args, **kwargs):
        """write_atr_rxval(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_base_write_atr_rxval(self, *args, **kwargs)

    def write_aux_dac(self, *args, **kwargs):
        """write_aux_dac(self, int which_side, int which_dac, int value) -> bool"""
        return _usrp_swig.usrp_base_write_aux_dac(self, *args, **kwargs)

    def read_aux_adc(self, *args, **kwargs):
        """read_aux_adc(self, int which_side, int which_adc) -> int"""
        return _usrp_swig.usrp_base_read_aux_adc(self, *args, **kwargs)

    def converter_rate(self):
        """converter_rate(self) -> long"""
        return _usrp_swig.usrp_base_converter_rate(self)

    def _set_led(self, *args, **kwargs):
        """_set_led(self, int which_led, bool on) -> bool"""
        return _usrp_swig.usrp_base__set_led(self, *args, **kwargs)

    def _write_fpga_reg(self, *args, **kwargs):
        """_write_fpga_reg(self, int regno, int value) -> bool"""
        return _usrp_swig.usrp_base__write_fpga_reg(self, *args, **kwargs)

    def _read_fpga_reg(self, *args, **kwargs):
        """_read_fpga_reg(self, int regno) -> int"""
        return _usrp_swig.usrp_base__read_fpga_reg(self, *args, **kwargs)

    def _write_fpga_reg_masked(self, *args, **kwargs):
        """_write_fpga_reg_masked(self, int regno, int value, int mask) -> bool"""
        return _usrp_swig.usrp_base__write_fpga_reg_masked(self, *args, **kwargs)

    def _write_9862(self, *args, **kwargs):
        """_write_9862(self, int which_codec, int regno, unsigned char value) -> bool"""
        return _usrp_swig.usrp_base__write_9862(self, *args, **kwargs)

    def _read_9862(self, *args, **kwargs):
        """_read_9862(self, int which_codec, int regno) -> int"""
        return _usrp_swig.usrp_base__read_9862(self, *args, **kwargs)

    def _write_spi(self, *args, **kwargs):
        """_write_spi(self, int optional_header, int enables, int format, string buf) -> bool"""
        return _usrp_swig.usrp_base__write_spi(self, *args, **kwargs)

    def _read_spi(self, *args, **kwargs):
        """_read_spi(self, int optional_header, int enables, int format, int len) -> string"""
        return _usrp_swig.usrp_base__read_spi(self, *args, **kwargs)

    def _real_pick_subdev(self, *args, **kwargs):
        """_real_pick_subdev(self, __dummy_3__ candidates = std::vector< int >(0)) -> usrp_subdev_spec"""
        return _usrp_swig.usrp_base__real_pick_subdev(self, *args, **kwargs)

    __swig_destroy__ = _usrp_swig.delete_usrp_base
    __del__ = lambda self : None;
usrp_base_swigregister = _usrp_swig.usrp_base_swigregister
usrp_base_swigregister(usrp_base)

class usrp_source_base(usrp_base):
    """Proxy of C++ usrp_source_base class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    def __init__(self, *args, **kwargs): raise AttributeError("No constructor defined")
    __repr__ = _swig_repr
    def set_decim_rate(self, *args, **kwargs):
        """set_decim_rate(self, unsigned int rate) -> bool"""
        return _usrp_swig.usrp_source_base_set_decim_rate(self, *args, **kwargs)

    def set_nchannels(self, *args, **kwargs):
        """set_nchannels(self, int nchan) -> bool"""
        return _usrp_swig.usrp_source_base_set_nchannels(self, *args, **kwargs)

    def set_mux(self, *args, **kwargs):
        """set_mux(self, int mux) -> bool"""
        return _usrp_swig.usrp_source_base_set_mux(self, *args, **kwargs)

    def _real_determine_rx_mux_value(self, *args):
        """
        _real_determine_rx_mux_value(self, usrp_subdev_spec ss) -> int
        _real_determine_rx_mux_value(self, usrp_subdev_spec ss_a, usrp_subdev_spec ss_b) -> int
        """
        return _usrp_swig.usrp_source_base__real_determine_rx_mux_value(self, *args)

    def set_rx_freq(self, *args, **kwargs):
        """set_rx_freq(self, int channel, double freq) -> bool"""
        return _usrp_swig.usrp_source_base_set_rx_freq(self, *args, **kwargs)

    def set_fpga_mode(self, *args, **kwargs):
        """set_fpga_mode(self, int mode) -> bool"""
        return _usrp_swig.usrp_source_base_set_fpga_mode(self, *args, **kwargs)

    def set_ddc_phase(self, *args, **kwargs):
        """set_ddc_phase(self, int channel, int phase) -> bool"""
        return _usrp_swig.usrp_source_base_set_ddc_phase(self, *args, **kwargs)

    def adc_rate(self):
        """adc_rate(self) -> long"""
        return _usrp_swig.usrp_source_base_adc_rate(self)

    def adc_freq(self):
        """adc_freq(self) -> long"""
        return _usrp_swig.usrp_source_base_adc_freq(self)

    def decim_rate(self):
        """decim_rate(self) -> unsigned int"""
        return _usrp_swig.usrp_source_base_decim_rate(self)

    def nchannels(self):
        """nchannels(self) -> int"""
        return _usrp_swig.usrp_source_base_nchannels(self)

    def mux(self):
        """mux(self) -> int"""
        return _usrp_swig.usrp_source_base_mux(self)

    def rx_freq(self, *args, **kwargs):
        """rx_freq(self, int channel) -> double"""
        return _usrp_swig.usrp_source_base_rx_freq(self, *args, **kwargs)

    def noverruns(self):
        """noverruns(self) -> int"""
        return _usrp_swig.usrp_source_base_noverruns(self)

    def has_rx_halfband(self):
        """has_rx_halfband(self) -> bool"""
        return _usrp_swig.usrp_source_base_has_rx_halfband(self)

    def has_tx_halfband(self):
        """has_tx_halfband(self) -> bool"""
        return _usrp_swig.usrp_source_base_has_tx_halfband(self)

    def nddcs(self):
        """nddcs(self) -> int"""
        return _usrp_swig.usrp_source_base_nddcs(self)

    def nducs(self):
        """nducs(self) -> int"""
        return _usrp_swig.usrp_source_base_nducs(self)

    def set_format(self, *args, **kwargs):
        """set_format(self, unsigned int format) -> bool"""
        return _usrp_swig.usrp_source_base_set_format(self, *args, **kwargs)

    def make_format(width = 16, shift = 0, want_q = True, bypass_halfband = False):
        """
        make_format(int width = 16, int shift = 0, bool want_q = True, 
            bool bypass_halfband = False) -> unsigned int
        """
        return _usrp_swig.usrp_source_base_make_format(width, shift, want_q, bypass_halfband)

    make_format = staticmethod(make_format)
    def format_width(*args, **kwargs):
        """format_width(unsigned int format) -> int"""
        return _usrp_swig.usrp_source_base_format_width(*args, **kwargs)

    format_width = staticmethod(format_width)
    def format_shift(*args, **kwargs):
        """format_shift(unsigned int format) -> int"""
        return _usrp_swig.usrp_source_base_format_shift(*args, **kwargs)

    format_shift = staticmethod(format_shift)
    def format_want_q(*args, **kwargs):
        """format_want_q(unsigned int format) -> bool"""
        return _usrp_swig.usrp_source_base_format_want_q(*args, **kwargs)

    format_want_q = staticmethod(format_want_q)
    def format_bypass_halfband(*args, **kwargs):
        """format_bypass_halfband(unsigned int format) -> bool"""
        return _usrp_swig.usrp_source_base_format_bypass_halfband(*args, **kwargs)

    format_bypass_halfband = staticmethod(format_bypass_halfband)
    def _real_tune(self, *args, **kwargs):
        """_real_tune(self, int chan, db_base_sptr db, double target_freq, usrp_tune_result result) -> bool"""
        return _usrp_swig.usrp_source_base__real_tune(self, *args, **kwargs)

    def _real_pick_rx_subdevice(self):
        """_real_pick_rx_subdevice(self) -> usrp_subdev_spec"""
        return _usrp_swig.usrp_source_base__real_pick_rx_subdevice(self)

    __swig_destroy__ = _usrp_swig.delete_usrp_source_base
    __del__ = lambda self : None;
usrp_source_base_swigregister = _usrp_swig.usrp_source_base_swigregister
usrp_source_base_swigregister(usrp_source_base)

def usrp_source_base_make_format(width = 16, shift = 0, want_q = True, bypass_halfband = False):
  """
    usrp_source_base_make_format(int width = 16, int shift = 0, bool want_q = True, 
        bool bypass_halfband = False) -> unsigned int
    """
  return _usrp_swig.usrp_source_base_make_format(width, shift, want_q, bypass_halfband)

def usrp_source_base_format_width(*args, **kwargs):
  """usrp_source_base_format_width(unsigned int format) -> int"""
  return _usrp_swig.usrp_source_base_format_width(*args, **kwargs)

def usrp_source_base_format_shift(*args, **kwargs):
  """usrp_source_base_format_shift(unsigned int format) -> int"""
  return _usrp_swig.usrp_source_base_format_shift(*args, **kwargs)

def usrp_source_base_format_want_q(*args, **kwargs):
  """usrp_source_base_format_want_q(unsigned int format) -> bool"""
  return _usrp_swig.usrp_source_base_format_want_q(*args, **kwargs)

def usrp_source_base_format_bypass_halfband(*args, **kwargs):
  """usrp_source_base_format_bypass_halfband(unsigned int format) -> bool"""
  return _usrp_swig.usrp_source_base_format_bypass_halfband(*args, **kwargs)

class usrp_source_c_sptr(object):
    """Proxy of C++ boost::shared_ptr<(usrp_source_c)> class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    def __init__(self, *args): 
        """
        __init__(self) -> usrp_source_c_sptr
        __init__(self,  p) -> usrp_source_c_sptr
        """
        this = _usrp_swig.new_usrp_source_c_sptr(*args)
        try: self.this.append(this)
        except: self.this = this
    def __deref__(self):
        """__deref__(self)"""
        return _usrp_swig.usrp_source_c_sptr___deref__(self)

    __swig_destroy__ = _usrp_swig.delete_usrp_source_c_sptr
    __del__ = lambda self : None;
    def set_decim_rate(self, *args, **kwargs):
        """set_decim_rate(self, unsigned int rate) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_set_decim_rate(self, *args, **kwargs)

    def set_nchannels(self, *args, **kwargs):
        """set_nchannels(self, int nchan) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_set_nchannels(self, *args, **kwargs)

    def set_mux(self, *args, **kwargs):
        """set_mux(self, int mux) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_set_mux(self, *args, **kwargs)

    def _real_determine_rx_mux_value(self, *args):
        """
        _real_determine_rx_mux_value(self, usrp_subdev_spec ss) -> int
        _real_determine_rx_mux_value(self, usrp_subdev_spec ss_a, usrp_subdev_spec ss_b) -> int
        """
        return _usrp_swig.usrp_source_c_sptr__real_determine_rx_mux_value(self, *args)

    def set_rx_freq(self, *args, **kwargs):
        """set_rx_freq(self, int channel, double freq) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_set_rx_freq(self, *args, **kwargs)

    def set_fpga_mode(self, *args, **kwargs):
        """set_fpga_mode(self, int mode) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_set_fpga_mode(self, *args, **kwargs)

    def set_ddc_phase(self, *args, **kwargs):
        """set_ddc_phase(self, int channel, int phase) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_set_ddc_phase(self, *args, **kwargs)

    def adc_rate(self):
        """adc_rate(self) -> long"""
        return _usrp_swig.usrp_source_c_sptr_adc_rate(self)

    def adc_freq(self):
        """adc_freq(self) -> long"""
        return _usrp_swig.usrp_source_c_sptr_adc_freq(self)

    def decim_rate(self):
        """decim_rate(self) -> unsigned int"""
        return _usrp_swig.usrp_source_c_sptr_decim_rate(self)

    def nchannels(self):
        """nchannels(self) -> int"""
        return _usrp_swig.usrp_source_c_sptr_nchannels(self)

    def mux(self):
        """mux(self) -> int"""
        return _usrp_swig.usrp_source_c_sptr_mux(self)

    def rx_freq(self, *args, **kwargs):
        """rx_freq(self, int channel) -> double"""
        return _usrp_swig.usrp_source_c_sptr_rx_freq(self, *args, **kwargs)

    def noverruns(self):
        """noverruns(self) -> int"""
        return _usrp_swig.usrp_source_c_sptr_noverruns(self)

    def has_rx_halfband(self):
        """has_rx_halfband(self) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_has_rx_halfband(self)

    def has_tx_halfband(self):
        """has_tx_halfband(self) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_has_tx_halfband(self)

    def nddcs(self):
        """nddcs(self) -> int"""
        return _usrp_swig.usrp_source_c_sptr_nddcs(self)

    def nducs(self):
        """nducs(self) -> int"""
        return _usrp_swig.usrp_source_c_sptr_nducs(self)

    def set_format(self, *args, **kwargs):
        """set_format(self, unsigned int format) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_set_format(self, *args, **kwargs)

    def make_format(self, width = 16, shift = 0, want_q = True, bypass_halfband = False):
        """
        make_format(self, int width = 16, int shift = 0, bool want_q = True, 
            bool bypass_halfband = False) -> unsigned int
        """
        return _usrp_swig.usrp_source_c_sptr_make_format(self, width, shift, want_q, bypass_halfband)

    def format_width(self, *args, **kwargs):
        """format_width(self, unsigned int format) -> int"""
        return _usrp_swig.usrp_source_c_sptr_format_width(self, *args, **kwargs)

    def format_shift(self, *args, **kwargs):
        """format_shift(self, unsigned int format) -> int"""
        return _usrp_swig.usrp_source_c_sptr_format_shift(self, *args, **kwargs)

    def format_want_q(self, *args, **kwargs):
        """format_want_q(self, unsigned int format) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_format_want_q(self, *args, **kwargs)

    def format_bypass_halfband(self, *args, **kwargs):
        """format_bypass_halfband(self, unsigned int format) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_format_bypass_halfband(self, *args, **kwargs)

    def _real_tune(self, *args, **kwargs):
        """_real_tune(self, int chan, db_base_sptr db, double target_freq, usrp_tune_result result) -> bool"""
        return _usrp_swig.usrp_source_c_sptr__real_tune(self, *args, **kwargs)

    def _real_pick_rx_subdevice(self):
        """_real_pick_rx_subdevice(self) -> usrp_subdev_spec"""
        return _usrp_swig.usrp_source_c_sptr__real_pick_rx_subdevice(self)

    def db(self, *args):
        """
        db(self) -> db_base_sptr_vector_vector
        db(self, int which_side) -> db_base_sptr_vector
        db(self, int which_side, int which_dev) -> db_base_sptr
        """
        return _usrp_swig.usrp_source_c_sptr_db(self, *args)

    def _real_selected_subdev(self, *args, **kwargs):
        """_real_selected_subdev(self, usrp_subdev_spec ss) -> db_base_sptr"""
        return _usrp_swig.usrp_source_c_sptr__real_selected_subdev(self, *args, **kwargs)

    def fpga_master_clock_freq(self):
        """fpga_master_clock_freq(self) -> long"""
        return _usrp_swig.usrp_source_c_sptr_fpga_master_clock_freq(self)

    def set_fpga_master_clock_freq(self, *args, **kwargs):
        """set_fpga_master_clock_freq(self, long master_clock)"""
        return _usrp_swig.usrp_source_c_sptr_set_fpga_master_clock_freq(self, *args, **kwargs)

    def set_verbose(self, *args, **kwargs):
        """set_verbose(self, bool on)"""
        return _usrp_swig.usrp_source_c_sptr_set_verbose(self, *args, **kwargs)

    READ_FAILED = _swig_property(_usrp_swig.usrp_source_c_sptr_READ_FAILED_get)
    def write_eeprom(self, *args, **kwargs):
        """write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_write_eeprom(self, *args, **kwargs)

    def read_eeprom(self, *args, **kwargs):
        """read_eeprom(self, int i2c_addr, int eeprom_offset, int len) -> string"""
        return _usrp_swig.usrp_source_c_sptr_read_eeprom(self, *args, **kwargs)

    def write_i2c(self, *args, **kwargs):
        """write_i2c(self, int i2c_addr, string buf) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_write_i2c(self, *args, **kwargs)

    def read_i2c(self, *args, **kwargs):
        """read_i2c(self, int i2c_addr, int len) -> string"""
        return _usrp_swig.usrp_source_c_sptr_read_i2c(self, *args, **kwargs)

    def set_adc_offset(self, *args, **kwargs):
        """set_adc_offset(self, int which_adc, int offset) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_set_adc_offset(self, *args, **kwargs)

    def set_dac_offset(self, *args, **kwargs):
        """set_dac_offset(self, int which_dac, int offset, int offset_pin) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_set_dac_offset(self, *args, **kwargs)

    def set_adc_buffer_bypass(self, *args, **kwargs):
        """set_adc_buffer_bypass(self, int which_adc, bool bypass) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_set_adc_buffer_bypass(self, *args, **kwargs)

    def set_dc_offset_cl_enable(self, *args, **kwargs):
        """set_dc_offset_cl_enable(self, int bits, int mask) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_set_dc_offset_cl_enable(self, *args, **kwargs)

    def serial_number(self):
        """serial_number(self) -> string"""
        return _usrp_swig.usrp_source_c_sptr_serial_number(self)

    def daughterboard_id(self, *args, **kwargs):
        """daughterboard_id(self, int which_side) -> int"""
        return _usrp_swig.usrp_source_c_sptr_daughterboard_id(self, *args, **kwargs)

    def write_atr_tx_delay(self, *args, **kwargs):
        """write_atr_tx_delay(self, int value) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_write_atr_tx_delay(self, *args, **kwargs)

    def write_atr_rx_delay(self, *args, **kwargs):
        """write_atr_rx_delay(self, int value) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_write_atr_rx_delay(self, *args, **kwargs)

    def set_pga(self, *args, **kwargs):
        """set_pga(self, int which_amp, double gain_in_db) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_set_pga(self, *args, **kwargs)

    def pga(self, *args, **kwargs):
        """pga(self, int which_amp) -> double"""
        return _usrp_swig.usrp_source_c_sptr_pga(self, *args, **kwargs)

    def pga_min(self):
        """pga_min(self) -> double"""
        return _usrp_swig.usrp_source_c_sptr_pga_min(self)

    def pga_max(self):
        """pga_max(self) -> double"""
        return _usrp_swig.usrp_source_c_sptr_pga_max(self)

    def pga_db_per_step(self):
        """pga_db_per_step(self) -> double"""
        return _usrp_swig.usrp_source_c_sptr_pga_db_per_step(self)

    def _write_oe(self, *args, **kwargs):
        """_write_oe(self, int which_side, int value, int mask) -> bool"""
        return _usrp_swig.usrp_source_c_sptr__write_oe(self, *args, **kwargs)

    def write_io(self, *args, **kwargs):
        """write_io(self, int which_side, int value, int mask) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_write_io(self, *args, **kwargs)

    def read_io(self, *args, **kwargs):
        """read_io(self, int which_side) -> int"""
        return _usrp_swig.usrp_source_c_sptr_read_io(self, *args, **kwargs)

    def write_atr_mask(self, *args, **kwargs):
        """write_atr_mask(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_write_atr_mask(self, *args, **kwargs)

    def write_atr_txval(self, *args, **kwargs):
        """write_atr_txval(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_write_atr_txval(self, *args, **kwargs)

    def write_atr_rxval(self, *args, **kwargs):
        """write_atr_rxval(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_write_atr_rxval(self, *args, **kwargs)

    def write_aux_dac(self, *args, **kwargs):
        """write_aux_dac(self, int which_side, int which_dac, int value) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_write_aux_dac(self, *args, **kwargs)

    def read_aux_adc(self, *args, **kwargs):
        """read_aux_adc(self, int which_side, int which_adc) -> int"""
        return _usrp_swig.usrp_source_c_sptr_read_aux_adc(self, *args, **kwargs)

    def converter_rate(self):
        """converter_rate(self) -> long"""
        return _usrp_swig.usrp_source_c_sptr_converter_rate(self)

    def _set_led(self, *args, **kwargs):
        """_set_led(self, int which_led, bool on) -> bool"""
        return _usrp_swig.usrp_source_c_sptr__set_led(self, *args, **kwargs)

    def _write_fpga_reg(self, *args, **kwargs):
        """_write_fpga_reg(self, int regno, int value) -> bool"""
        return _usrp_swig.usrp_source_c_sptr__write_fpga_reg(self, *args, **kwargs)

    def _read_fpga_reg(self, *args, **kwargs):
        """_read_fpga_reg(self, int regno) -> int"""
        return _usrp_swig.usrp_source_c_sptr__read_fpga_reg(self, *args, **kwargs)

    def _write_fpga_reg_masked(self, *args, **kwargs):
        """_write_fpga_reg_masked(self, int regno, int value, int mask) -> bool"""
        return _usrp_swig.usrp_source_c_sptr__write_fpga_reg_masked(self, *args, **kwargs)

    def _write_9862(self, *args, **kwargs):
        """_write_9862(self, int which_codec, int regno, unsigned char value) -> bool"""
        return _usrp_swig.usrp_source_c_sptr__write_9862(self, *args, **kwargs)

    def _read_9862(self, *args, **kwargs):
        """_read_9862(self, int which_codec, int regno) -> int"""
        return _usrp_swig.usrp_source_c_sptr__read_9862(self, *args, **kwargs)

    def _write_spi(self, *args, **kwargs):
        """_write_spi(self, int optional_header, int enables, int format, string buf) -> bool"""
        return _usrp_swig.usrp_source_c_sptr__write_spi(self, *args, **kwargs)

    def _read_spi(self, *args, **kwargs):
        """_read_spi(self, int optional_header, int enables, int format, int len) -> string"""
        return _usrp_swig.usrp_source_c_sptr__read_spi(self, *args, **kwargs)

    def _real_pick_subdev(self, *args, **kwargs):
        """_real_pick_subdev(self, __dummy_3__ candidates = std::vector< int >(0)) -> usrp_subdev_spec"""
        return _usrp_swig.usrp_source_c_sptr__real_pick_subdev(self, *args, **kwargs)

    def history(self):
        """history(self) -> unsigned int"""
        return _usrp_swig.usrp_source_c_sptr_history(self)

    def output_multiple(self):
        """output_multiple(self) -> int"""
        return _usrp_swig.usrp_source_c_sptr_output_multiple(self)

    def relative_rate(self):
        """relative_rate(self) -> double"""
        return _usrp_swig.usrp_source_c_sptr_relative_rate(self)

    def start(self):
        """start(self) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_start(self)

    def stop(self):
        """stop(self) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_stop(self)

    def detail(self):
        """detail(self) -> gr_block_detail_sptr"""
        return _usrp_swig.usrp_source_c_sptr_detail(self)

    def set_detail(self, *args, **kwargs):
        """set_detail(self, gr_block_detail_sptr detail)"""
        return _usrp_swig.usrp_source_c_sptr_set_detail(self, *args, **kwargs)

    def name(self):
        """name(self) -> string"""
        return _usrp_swig.usrp_source_c_sptr_name(self)

    def input_signature(self):
        """input_signature(self) -> gr_io_signature_sptr"""
        return _usrp_swig.usrp_source_c_sptr_input_signature(self)

    def output_signature(self):
        """output_signature(self) -> gr_io_signature_sptr"""
        return _usrp_swig.usrp_source_c_sptr_output_signature(self)

    def unique_id(self):
        """unique_id(self) -> long"""
        return _usrp_swig.usrp_source_c_sptr_unique_id(self)

    def basic_block(self):
        """basic_block(self) -> gr_basic_block_sptr"""
        return _usrp_swig.usrp_source_c_sptr_basic_block(self)

    def check_topology(self, *args, **kwargs):
        """check_topology(self, int ninputs, int noutputs) -> bool"""
        return _usrp_swig.usrp_source_c_sptr_check_topology(self, *args, **kwargs)

usrp_source_c_sptr_swigregister = _usrp_swig.usrp_source_c_sptr_swigregister
usrp_source_c_sptr_swigregister(usrp_source_c_sptr)

usrp_source_c_sptr.block = lambda self: usrp_source_c_block (self)
usrp_source_c_sptr.__repr__ = lambda self: "<gr_block %s (%d)>" % (self.name(), self.unique_id ())


def source_c(*args, **kwargs):
  """
    source_c(int which = 0, unsigned int decim_rate = 16, int nchan = 1, 
        int mux = -1, int mode = 0, int fusb_block_size = 0, 
        int fusb_nblocks = 0, string fpga_filename = "", 
        string firmware_filename = "") -> usrp_source_c_sptr
    """
  return _usrp_swig.source_c(*args, **kwargs)
class usrp_source_s_sptr(object):
    """Proxy of C++ boost::shared_ptr<(usrp_source_s)> class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    def __init__(self, *args): 
        """
        __init__(self) -> usrp_source_s_sptr
        __init__(self,  p) -> usrp_source_s_sptr
        """
        this = _usrp_swig.new_usrp_source_s_sptr(*args)
        try: self.this.append(this)
        except: self.this = this
    def __deref__(self):
        """__deref__(self)"""
        return _usrp_swig.usrp_source_s_sptr___deref__(self)

    __swig_destroy__ = _usrp_swig.delete_usrp_source_s_sptr
    __del__ = lambda self : None;
    def set_decim_rate(self, *args, **kwargs):
        """set_decim_rate(self, unsigned int rate) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_set_decim_rate(self, *args, **kwargs)

    def set_nchannels(self, *args, **kwargs):
        """set_nchannels(self, int nchan) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_set_nchannels(self, *args, **kwargs)

    def set_mux(self, *args, **kwargs):
        """set_mux(self, int mux) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_set_mux(self, *args, **kwargs)

    def _real_determine_rx_mux_value(self, *args):
        """
        _real_determine_rx_mux_value(self, usrp_subdev_spec ss) -> int
        _real_determine_rx_mux_value(self, usrp_subdev_spec ss_a, usrp_subdev_spec ss_b) -> int
        """
        return _usrp_swig.usrp_source_s_sptr__real_determine_rx_mux_value(self, *args)

    def set_rx_freq(self, *args, **kwargs):
        """set_rx_freq(self, int channel, double freq) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_set_rx_freq(self, *args, **kwargs)

    def set_fpga_mode(self, *args, **kwargs):
        """set_fpga_mode(self, int mode) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_set_fpga_mode(self, *args, **kwargs)

    def set_ddc_phase(self, *args, **kwargs):
        """set_ddc_phase(self, int channel, int phase) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_set_ddc_phase(self, *args, **kwargs)

    def adc_rate(self):
        """adc_rate(self) -> long"""
        return _usrp_swig.usrp_source_s_sptr_adc_rate(self)

    def adc_freq(self):
        """adc_freq(self) -> long"""
        return _usrp_swig.usrp_source_s_sptr_adc_freq(self)

    def decim_rate(self):
        """decim_rate(self) -> unsigned int"""
        return _usrp_swig.usrp_source_s_sptr_decim_rate(self)

    def nchannels(self):
        """nchannels(self) -> int"""
        return _usrp_swig.usrp_source_s_sptr_nchannels(self)

    def mux(self):
        """mux(self) -> int"""
        return _usrp_swig.usrp_source_s_sptr_mux(self)

    def rx_freq(self, *args, **kwargs):
        """rx_freq(self, int channel) -> double"""
        return _usrp_swig.usrp_source_s_sptr_rx_freq(self, *args, **kwargs)

    def noverruns(self):
        """noverruns(self) -> int"""
        return _usrp_swig.usrp_source_s_sptr_noverruns(self)

    def has_rx_halfband(self):
        """has_rx_halfband(self) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_has_rx_halfband(self)

    def has_tx_halfband(self):
        """has_tx_halfband(self) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_has_tx_halfband(self)

    def nddcs(self):
        """nddcs(self) -> int"""
        return _usrp_swig.usrp_source_s_sptr_nddcs(self)

    def nducs(self):
        """nducs(self) -> int"""
        return _usrp_swig.usrp_source_s_sptr_nducs(self)

    def set_format(self, *args, **kwargs):
        """set_format(self, unsigned int format) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_set_format(self, *args, **kwargs)

    def make_format(self, width = 16, shift = 0, want_q = True, bypass_halfband = False):
        """
        make_format(self, int width = 16, int shift = 0, bool want_q = True, 
            bool bypass_halfband = False) -> unsigned int
        """
        return _usrp_swig.usrp_source_s_sptr_make_format(self, width, shift, want_q, bypass_halfband)

    def format_width(self, *args, **kwargs):
        """format_width(self, unsigned int format) -> int"""
        return _usrp_swig.usrp_source_s_sptr_format_width(self, *args, **kwargs)

    def format_shift(self, *args, **kwargs):
        """format_shift(self, unsigned int format) -> int"""
        return _usrp_swig.usrp_source_s_sptr_format_shift(self, *args, **kwargs)

    def format_want_q(self, *args, **kwargs):
        """format_want_q(self, unsigned int format) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_format_want_q(self, *args, **kwargs)

    def format_bypass_halfband(self, *args, **kwargs):
        """format_bypass_halfband(self, unsigned int format) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_format_bypass_halfband(self, *args, **kwargs)

    def _real_tune(self, *args, **kwargs):
        """_real_tune(self, int chan, db_base_sptr db, double target_freq, usrp_tune_result result) -> bool"""
        return _usrp_swig.usrp_source_s_sptr__real_tune(self, *args, **kwargs)

    def _real_pick_rx_subdevice(self):
        """_real_pick_rx_subdevice(self) -> usrp_subdev_spec"""
        return _usrp_swig.usrp_source_s_sptr__real_pick_rx_subdevice(self)

    def db(self, *args):
        """
        db(self) -> db_base_sptr_vector_vector
        db(self, int which_side) -> db_base_sptr_vector
        db(self, int which_side, int which_dev) -> db_base_sptr
        """
        return _usrp_swig.usrp_source_s_sptr_db(self, *args)

    def _real_selected_subdev(self, *args, **kwargs):
        """_real_selected_subdev(self, usrp_subdev_spec ss) -> db_base_sptr"""
        return _usrp_swig.usrp_source_s_sptr__real_selected_subdev(self, *args, **kwargs)

    def fpga_master_clock_freq(self):
        """fpga_master_clock_freq(self) -> long"""
        return _usrp_swig.usrp_source_s_sptr_fpga_master_clock_freq(self)

    def set_fpga_master_clock_freq(self, *args, **kwargs):
        """set_fpga_master_clock_freq(self, long master_clock)"""
        return _usrp_swig.usrp_source_s_sptr_set_fpga_master_clock_freq(self, *args, **kwargs)

    def set_verbose(self, *args, **kwargs):
        """set_verbose(self, bool on)"""
        return _usrp_swig.usrp_source_s_sptr_set_verbose(self, *args, **kwargs)

    READ_FAILED = _swig_property(_usrp_swig.usrp_source_s_sptr_READ_FAILED_get)
    def write_eeprom(self, *args, **kwargs):
        """write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_write_eeprom(self, *args, **kwargs)

    def read_eeprom(self, *args, **kwargs):
        """read_eeprom(self, int i2c_addr, int eeprom_offset, int len) -> string"""
        return _usrp_swig.usrp_source_s_sptr_read_eeprom(self, *args, **kwargs)

    def write_i2c(self, *args, **kwargs):
        """write_i2c(self, int i2c_addr, string buf) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_write_i2c(self, *args, **kwargs)

    def read_i2c(self, *args, **kwargs):
        """read_i2c(self, int i2c_addr, int len) -> string"""
        return _usrp_swig.usrp_source_s_sptr_read_i2c(self, *args, **kwargs)

    def set_adc_offset(self, *args, **kwargs):
        """set_adc_offset(self, int which_adc, int offset) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_set_adc_offset(self, *args, **kwargs)

    def set_dac_offset(self, *args, **kwargs):
        """set_dac_offset(self, int which_dac, int offset, int offset_pin) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_set_dac_offset(self, *args, **kwargs)

    def set_adc_buffer_bypass(self, *args, **kwargs):
        """set_adc_buffer_bypass(self, int which_adc, bool bypass) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_set_adc_buffer_bypass(self, *args, **kwargs)

    def set_dc_offset_cl_enable(self, *args, **kwargs):
        """set_dc_offset_cl_enable(self, int bits, int mask) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_set_dc_offset_cl_enable(self, *args, **kwargs)

    def serial_number(self):
        """serial_number(self) -> string"""
        return _usrp_swig.usrp_source_s_sptr_serial_number(self)

    def daughterboard_id(self, *args, **kwargs):
        """daughterboard_id(self, int which_side) -> int"""
        return _usrp_swig.usrp_source_s_sptr_daughterboard_id(self, *args, **kwargs)

    def write_atr_tx_delay(self, *args, **kwargs):
        """write_atr_tx_delay(self, int value) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_write_atr_tx_delay(self, *args, **kwargs)

    def write_atr_rx_delay(self, *args, **kwargs):
        """write_atr_rx_delay(self, int value) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_write_atr_rx_delay(self, *args, **kwargs)

    def set_pga(self, *args, **kwargs):
        """set_pga(self, int which_amp, double gain_in_db) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_set_pga(self, *args, **kwargs)

    def pga(self, *args, **kwargs):
        """pga(self, int which_amp) -> double"""
        return _usrp_swig.usrp_source_s_sptr_pga(self, *args, **kwargs)

    def pga_min(self):
        """pga_min(self) -> double"""
        return _usrp_swig.usrp_source_s_sptr_pga_min(self)

    def pga_max(self):
        """pga_max(self) -> double"""
        return _usrp_swig.usrp_source_s_sptr_pga_max(self)

    def pga_db_per_step(self):
        """pga_db_per_step(self) -> double"""
        return _usrp_swig.usrp_source_s_sptr_pga_db_per_step(self)

    def _write_oe(self, *args, **kwargs):
        """_write_oe(self, int which_side, int value, int mask) -> bool"""
        return _usrp_swig.usrp_source_s_sptr__write_oe(self, *args, **kwargs)

    def write_io(self, *args, **kwargs):
        """write_io(self, int which_side, int value, int mask) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_write_io(self, *args, **kwargs)

    def read_io(self, *args, **kwargs):
        """read_io(self, int which_side) -> int"""
        return _usrp_swig.usrp_source_s_sptr_read_io(self, *args, **kwargs)

    def write_atr_mask(self, *args, **kwargs):
        """write_atr_mask(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_write_atr_mask(self, *args, **kwargs)

    def write_atr_txval(self, *args, **kwargs):
        """write_atr_txval(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_write_atr_txval(self, *args, **kwargs)

    def write_atr_rxval(self, *args, **kwargs):
        """write_atr_rxval(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_write_atr_rxval(self, *args, **kwargs)

    def write_aux_dac(self, *args, **kwargs):
        """write_aux_dac(self, int which_side, int which_dac, int value) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_write_aux_dac(self, *args, **kwargs)

    def read_aux_adc(self, *args, **kwargs):
        """read_aux_adc(self, int which_side, int which_adc) -> int"""
        return _usrp_swig.usrp_source_s_sptr_read_aux_adc(self, *args, **kwargs)

    def converter_rate(self):
        """converter_rate(self) -> long"""
        return _usrp_swig.usrp_source_s_sptr_converter_rate(self)

    def _set_led(self, *args, **kwargs):
        """_set_led(self, int which_led, bool on) -> bool"""
        return _usrp_swig.usrp_source_s_sptr__set_led(self, *args, **kwargs)

    def _write_fpga_reg(self, *args, **kwargs):
        """_write_fpga_reg(self, int regno, int value) -> bool"""
        return _usrp_swig.usrp_source_s_sptr__write_fpga_reg(self, *args, **kwargs)

    def _read_fpga_reg(self, *args, **kwargs):
        """_read_fpga_reg(self, int regno) -> int"""
        return _usrp_swig.usrp_source_s_sptr__read_fpga_reg(self, *args, **kwargs)

    def _write_fpga_reg_masked(self, *args, **kwargs):
        """_write_fpga_reg_masked(self, int regno, int value, int mask) -> bool"""
        return _usrp_swig.usrp_source_s_sptr__write_fpga_reg_masked(self, *args, **kwargs)

    def _write_9862(self, *args, **kwargs):
        """_write_9862(self, int which_codec, int regno, unsigned char value) -> bool"""
        return _usrp_swig.usrp_source_s_sptr__write_9862(self, *args, **kwargs)

    def _read_9862(self, *args, **kwargs):
        """_read_9862(self, int which_codec, int regno) -> int"""
        return _usrp_swig.usrp_source_s_sptr__read_9862(self, *args, **kwargs)

    def _write_spi(self, *args, **kwargs):
        """_write_spi(self, int optional_header, int enables, int format, string buf) -> bool"""
        return _usrp_swig.usrp_source_s_sptr__write_spi(self, *args, **kwargs)

    def _read_spi(self, *args, **kwargs):
        """_read_spi(self, int optional_header, int enables, int format, int len) -> string"""
        return _usrp_swig.usrp_source_s_sptr__read_spi(self, *args, **kwargs)

    def _real_pick_subdev(self, *args, **kwargs):
        """_real_pick_subdev(self, __dummy_3__ candidates = std::vector< int >(0)) -> usrp_subdev_spec"""
        return _usrp_swig.usrp_source_s_sptr__real_pick_subdev(self, *args, **kwargs)

    def history(self):
        """history(self) -> unsigned int"""
        return _usrp_swig.usrp_source_s_sptr_history(self)

    def output_multiple(self):
        """output_multiple(self) -> int"""
        return _usrp_swig.usrp_source_s_sptr_output_multiple(self)

    def relative_rate(self):
        """relative_rate(self) -> double"""
        return _usrp_swig.usrp_source_s_sptr_relative_rate(self)

    def start(self):
        """start(self) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_start(self)

    def stop(self):
        """stop(self) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_stop(self)

    def detail(self):
        """detail(self) -> gr_block_detail_sptr"""
        return _usrp_swig.usrp_source_s_sptr_detail(self)

    def set_detail(self, *args, **kwargs):
        """set_detail(self, gr_block_detail_sptr detail)"""
        return _usrp_swig.usrp_source_s_sptr_set_detail(self, *args, **kwargs)

    def name(self):
        """name(self) -> string"""
        return _usrp_swig.usrp_source_s_sptr_name(self)

    def input_signature(self):
        """input_signature(self) -> gr_io_signature_sptr"""
        return _usrp_swig.usrp_source_s_sptr_input_signature(self)

    def output_signature(self):
        """output_signature(self) -> gr_io_signature_sptr"""
        return _usrp_swig.usrp_source_s_sptr_output_signature(self)

    def unique_id(self):
        """unique_id(self) -> long"""
        return _usrp_swig.usrp_source_s_sptr_unique_id(self)

    def basic_block(self):
        """basic_block(self) -> gr_basic_block_sptr"""
        return _usrp_swig.usrp_source_s_sptr_basic_block(self)

    def check_topology(self, *args, **kwargs):
        """check_topology(self, int ninputs, int noutputs) -> bool"""
        return _usrp_swig.usrp_source_s_sptr_check_topology(self, *args, **kwargs)

usrp_source_s_sptr_swigregister = _usrp_swig.usrp_source_s_sptr_swigregister
usrp_source_s_sptr_swigregister(usrp_source_s_sptr)

usrp_source_s_sptr.block = lambda self: usrp_source_s_block (self)
usrp_source_s_sptr.__repr__ = lambda self: "<gr_block %s (%d)>" % (self.name(), self.unique_id ())


def source_s(*args, **kwargs):
  """
    source_s(int which = 0, unsigned int decim_rate = 16, int nchan = 1, 
        int mux = -1, int mode = 0, int fusb_block_size = 0, 
        int fusb_nblocks = 0, string fpga_filename = "", 
        string firmware_filename = "") -> usrp_source_s_sptr
    """
  return _usrp_swig.source_s(*args, **kwargs)
class usrp_sink_base(usrp_base):
    """Proxy of C++ usrp_sink_base class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    def __init__(self, *args, **kwargs): raise AttributeError("No constructor defined")
    __repr__ = _swig_repr
    def set_interp_rate(self, *args, **kwargs):
        """set_interp_rate(self, unsigned int rate) -> bool"""
        return _usrp_swig.usrp_sink_base_set_interp_rate(self, *args, **kwargs)

    def set_nchannels(self, *args, **kwargs):
        """set_nchannels(self, int nchan) -> bool"""
        return _usrp_swig.usrp_sink_base_set_nchannels(self, *args, **kwargs)

    def set_mux(self, *args, **kwargs):
        """set_mux(self, int mux) -> bool"""
        return _usrp_swig.usrp_sink_base_set_mux(self, *args, **kwargs)

    def _real_determine_tx_mux_value(self, *args):
        """
        _real_determine_tx_mux_value(self, usrp_subdev_spec ss) -> int
        _real_determine_tx_mux_value(self, usrp_subdev_spec ss_a, usrp_subdev_spec ss_b) -> int
        """
        return _usrp_swig.usrp_sink_base__real_determine_tx_mux_value(self, *args)

    def set_tx_freq(self, *args, **kwargs):
        """set_tx_freq(self, int channel, double freq) -> bool"""
        return _usrp_swig.usrp_sink_base_set_tx_freq(self, *args, **kwargs)

    def dac_rate(self):
        """dac_rate(self) -> long"""
        return _usrp_swig.usrp_sink_base_dac_rate(self)

    def dac_freq(self):
        """dac_freq(self) -> long"""
        return _usrp_swig.usrp_sink_base_dac_freq(self)

    def interp_rate(self):
        """interp_rate(self) -> unsigned int"""
        return _usrp_swig.usrp_sink_base_interp_rate(self)

    def nchannels(self):
        """nchannels(self) -> int"""
        return _usrp_swig.usrp_sink_base_nchannels(self)

    def mux(self):
        """mux(self) -> int"""
        return _usrp_swig.usrp_sink_base_mux(self)

    def tx_freq(self, *args, **kwargs):
        """tx_freq(self, int channel) -> double"""
        return _usrp_swig.usrp_sink_base_tx_freq(self, *args, **kwargs)

    def nunderruns(self):
        """nunderruns(self) -> int"""
        return _usrp_swig.usrp_sink_base_nunderruns(self)

    def has_rx_halfband(self):
        """has_rx_halfband(self) -> bool"""
        return _usrp_swig.usrp_sink_base_has_rx_halfband(self)

    def has_tx_halfband(self):
        """has_tx_halfband(self) -> bool"""
        return _usrp_swig.usrp_sink_base_has_tx_halfband(self)

    def nddcs(self):
        """nddcs(self) -> int"""
        return _usrp_swig.usrp_sink_base_nddcs(self)

    def nducs(self):
        """nducs(self) -> int"""
        return _usrp_swig.usrp_sink_base_nducs(self)

    def _real_tune(self, *args, **kwargs):
        """_real_tune(self, int chan, db_base_sptr db, double target_freq, usrp_tune_result result) -> bool"""
        return _usrp_swig.usrp_sink_base__real_tune(self, *args, **kwargs)

    def _real_pick_tx_subdevice(self):
        """_real_pick_tx_subdevice(self) -> usrp_subdev_spec"""
        return _usrp_swig.usrp_sink_base__real_pick_tx_subdevice(self)

    __swig_destroy__ = _usrp_swig.delete_usrp_sink_base
    __del__ = lambda self : None;
usrp_sink_base_swigregister = _usrp_swig.usrp_sink_base_swigregister
usrp_sink_base_swigregister(usrp_sink_base)

class usrp_sink_c_sptr(object):
    """Proxy of C++ boost::shared_ptr<(usrp_sink_c)> class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    def __init__(self, *args): 
        """
        __init__(self) -> usrp_sink_c_sptr
        __init__(self,  p) -> usrp_sink_c_sptr
        """
        this = _usrp_swig.new_usrp_sink_c_sptr(*args)
        try: self.this.append(this)
        except: self.this = this
    def __deref__(self):
        """__deref__(self)"""
        return _usrp_swig.usrp_sink_c_sptr___deref__(self)

    __swig_destroy__ = _usrp_swig.delete_usrp_sink_c_sptr
    __del__ = lambda self : None;
    def set_interp_rate(self, *args, **kwargs):
        """set_interp_rate(self, unsigned int rate) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_set_interp_rate(self, *args, **kwargs)

    def set_nchannels(self, *args, **kwargs):
        """set_nchannels(self, int nchan) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_set_nchannels(self, *args, **kwargs)

    def set_mux(self, *args, **kwargs):
        """set_mux(self, int mux) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_set_mux(self, *args, **kwargs)

    def _real_determine_tx_mux_value(self, *args):
        """
        _real_determine_tx_mux_value(self, usrp_subdev_spec ss) -> int
        _real_determine_tx_mux_value(self, usrp_subdev_spec ss_a, usrp_subdev_spec ss_b) -> int
        """
        return _usrp_swig.usrp_sink_c_sptr__real_determine_tx_mux_value(self, *args)

    def set_tx_freq(self, *args, **kwargs):
        """set_tx_freq(self, int channel, double freq) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_set_tx_freq(self, *args, **kwargs)

    def dac_rate(self):
        """dac_rate(self) -> long"""
        return _usrp_swig.usrp_sink_c_sptr_dac_rate(self)

    def dac_freq(self):
        """dac_freq(self) -> long"""
        return _usrp_swig.usrp_sink_c_sptr_dac_freq(self)

    def interp_rate(self):
        """interp_rate(self) -> unsigned int"""
        return _usrp_swig.usrp_sink_c_sptr_interp_rate(self)

    def nchannels(self):
        """nchannels(self) -> int"""
        return _usrp_swig.usrp_sink_c_sptr_nchannels(self)

    def mux(self):
        """mux(self) -> int"""
        return _usrp_swig.usrp_sink_c_sptr_mux(self)

    def tx_freq(self, *args, **kwargs):
        """tx_freq(self, int channel) -> double"""
        return _usrp_swig.usrp_sink_c_sptr_tx_freq(self, *args, **kwargs)

    def nunderruns(self):
        """nunderruns(self) -> int"""
        return _usrp_swig.usrp_sink_c_sptr_nunderruns(self)

    def has_rx_halfband(self):
        """has_rx_halfband(self) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_has_rx_halfband(self)

    def has_tx_halfband(self):
        """has_tx_halfband(self) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_has_tx_halfband(self)

    def nddcs(self):
        """nddcs(self) -> int"""
        return _usrp_swig.usrp_sink_c_sptr_nddcs(self)

    def nducs(self):
        """nducs(self) -> int"""
        return _usrp_swig.usrp_sink_c_sptr_nducs(self)

    def _real_tune(self, *args, **kwargs):
        """_real_tune(self, int chan, db_base_sptr db, double target_freq, usrp_tune_result result) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr__real_tune(self, *args, **kwargs)

    def _real_pick_tx_subdevice(self):
        """_real_pick_tx_subdevice(self) -> usrp_subdev_spec"""
        return _usrp_swig.usrp_sink_c_sptr__real_pick_tx_subdevice(self)

    def db(self, *args):
        """
        db(self) -> db_base_sptr_vector_vector
        db(self, int which_side) -> db_base_sptr_vector
        db(self, int which_side, int which_dev) -> db_base_sptr
        """
        return _usrp_swig.usrp_sink_c_sptr_db(self, *args)

    def _real_selected_subdev(self, *args, **kwargs):
        """_real_selected_subdev(self, usrp_subdev_spec ss) -> db_base_sptr"""
        return _usrp_swig.usrp_sink_c_sptr__real_selected_subdev(self, *args, **kwargs)

    def fpga_master_clock_freq(self):
        """fpga_master_clock_freq(self) -> long"""
        return _usrp_swig.usrp_sink_c_sptr_fpga_master_clock_freq(self)

    def set_fpga_master_clock_freq(self, *args, **kwargs):
        """set_fpga_master_clock_freq(self, long master_clock)"""
        return _usrp_swig.usrp_sink_c_sptr_set_fpga_master_clock_freq(self, *args, **kwargs)

    def set_verbose(self, *args, **kwargs):
        """set_verbose(self, bool on)"""
        return _usrp_swig.usrp_sink_c_sptr_set_verbose(self, *args, **kwargs)

    READ_FAILED = _swig_property(_usrp_swig.usrp_sink_c_sptr_READ_FAILED_get)
    def write_eeprom(self, *args, **kwargs):
        """write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_write_eeprom(self, *args, **kwargs)

    def read_eeprom(self, *args, **kwargs):
        """read_eeprom(self, int i2c_addr, int eeprom_offset, int len) -> string"""
        return _usrp_swig.usrp_sink_c_sptr_read_eeprom(self, *args, **kwargs)

    def write_i2c(self, *args, **kwargs):
        """write_i2c(self, int i2c_addr, string buf) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_write_i2c(self, *args, **kwargs)

    def read_i2c(self, *args, **kwargs):
        """read_i2c(self, int i2c_addr, int len) -> string"""
        return _usrp_swig.usrp_sink_c_sptr_read_i2c(self, *args, **kwargs)

    def set_adc_offset(self, *args, **kwargs):
        """set_adc_offset(self, int which_adc, int offset) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_set_adc_offset(self, *args, **kwargs)

    def set_dac_offset(self, *args, **kwargs):
        """set_dac_offset(self, int which_dac, int offset, int offset_pin) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_set_dac_offset(self, *args, **kwargs)

    def set_adc_buffer_bypass(self, *args, **kwargs):
        """set_adc_buffer_bypass(self, int which_adc, bool bypass) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_set_adc_buffer_bypass(self, *args, **kwargs)

    def set_dc_offset_cl_enable(self, *args, **kwargs):
        """set_dc_offset_cl_enable(self, int bits, int mask) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_set_dc_offset_cl_enable(self, *args, **kwargs)

    def serial_number(self):
        """serial_number(self) -> string"""
        return _usrp_swig.usrp_sink_c_sptr_serial_number(self)

    def daughterboard_id(self, *args, **kwargs):
        """daughterboard_id(self, int which_side) -> int"""
        return _usrp_swig.usrp_sink_c_sptr_daughterboard_id(self, *args, **kwargs)

    def write_atr_tx_delay(self, *args, **kwargs):
        """write_atr_tx_delay(self, int value) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_write_atr_tx_delay(self, *args, **kwargs)

    def write_atr_rx_delay(self, *args, **kwargs):
        """write_atr_rx_delay(self, int value) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_write_atr_rx_delay(self, *args, **kwargs)

    def set_pga(self, *args, **kwargs):
        """set_pga(self, int which_amp, double gain_in_db) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_set_pga(self, *args, **kwargs)

    def pga(self, *args, **kwargs):
        """pga(self, int which_amp) -> double"""
        return _usrp_swig.usrp_sink_c_sptr_pga(self, *args, **kwargs)

    def pga_min(self):
        """pga_min(self) -> double"""
        return _usrp_swig.usrp_sink_c_sptr_pga_min(self)

    def pga_max(self):
        """pga_max(self) -> double"""
        return _usrp_swig.usrp_sink_c_sptr_pga_max(self)

    def pga_db_per_step(self):
        """pga_db_per_step(self) -> double"""
        return _usrp_swig.usrp_sink_c_sptr_pga_db_per_step(self)

    def _write_oe(self, *args, **kwargs):
        """_write_oe(self, int which_side, int value, int mask) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr__write_oe(self, *args, **kwargs)

    def write_io(self, *args, **kwargs):
        """write_io(self, int which_side, int value, int mask) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_write_io(self, *args, **kwargs)

    def read_io(self, *args, **kwargs):
        """read_io(self, int which_side) -> int"""
        return _usrp_swig.usrp_sink_c_sptr_read_io(self, *args, **kwargs)

    def write_atr_mask(self, *args, **kwargs):
        """write_atr_mask(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_write_atr_mask(self, *args, **kwargs)

    def write_atr_txval(self, *args, **kwargs):
        """write_atr_txval(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_write_atr_txval(self, *args, **kwargs)

    def write_atr_rxval(self, *args, **kwargs):
        """write_atr_rxval(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_write_atr_rxval(self, *args, **kwargs)

    def write_aux_dac(self, *args, **kwargs):
        """write_aux_dac(self, int which_side, int which_dac, int value) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_write_aux_dac(self, *args, **kwargs)

    def read_aux_adc(self, *args, **kwargs):
        """read_aux_adc(self, int which_side, int which_adc) -> int"""
        return _usrp_swig.usrp_sink_c_sptr_read_aux_adc(self, *args, **kwargs)

    def converter_rate(self):
        """converter_rate(self) -> long"""
        return _usrp_swig.usrp_sink_c_sptr_converter_rate(self)

    def _set_led(self, *args, **kwargs):
        """_set_led(self, int which_led, bool on) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr__set_led(self, *args, **kwargs)

    def _write_fpga_reg(self, *args, **kwargs):
        """_write_fpga_reg(self, int regno, int value) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr__write_fpga_reg(self, *args, **kwargs)

    def _read_fpga_reg(self, *args, **kwargs):
        """_read_fpga_reg(self, int regno) -> int"""
        return _usrp_swig.usrp_sink_c_sptr__read_fpga_reg(self, *args, **kwargs)

    def _write_fpga_reg_masked(self, *args, **kwargs):
        """_write_fpga_reg_masked(self, int regno, int value, int mask) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr__write_fpga_reg_masked(self, *args, **kwargs)

    def _write_9862(self, *args, **kwargs):
        """_write_9862(self, int which_codec, int regno, unsigned char value) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr__write_9862(self, *args, **kwargs)

    def _read_9862(self, *args, **kwargs):
        """_read_9862(self, int which_codec, int regno) -> int"""
        return _usrp_swig.usrp_sink_c_sptr__read_9862(self, *args, **kwargs)

    def _write_spi(self, *args, **kwargs):
        """_write_spi(self, int optional_header, int enables, int format, string buf) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr__write_spi(self, *args, **kwargs)

    def _read_spi(self, *args, **kwargs):
        """_read_spi(self, int optional_header, int enables, int format, int len) -> string"""
        return _usrp_swig.usrp_sink_c_sptr__read_spi(self, *args, **kwargs)

    def _real_pick_subdev(self, *args, **kwargs):
        """_real_pick_subdev(self, __dummy_3__ candidates = std::vector< int >(0)) -> usrp_subdev_spec"""
        return _usrp_swig.usrp_sink_c_sptr__real_pick_subdev(self, *args, **kwargs)

    def history(self):
        """history(self) -> unsigned int"""
        return _usrp_swig.usrp_sink_c_sptr_history(self)

    def output_multiple(self):
        """output_multiple(self) -> int"""
        return _usrp_swig.usrp_sink_c_sptr_output_multiple(self)

    def relative_rate(self):
        """relative_rate(self) -> double"""
        return _usrp_swig.usrp_sink_c_sptr_relative_rate(self)

    def start(self):
        """start(self) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_start(self)

    def stop(self):
        """stop(self) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_stop(self)

    def detail(self):
        """detail(self) -> gr_block_detail_sptr"""
        return _usrp_swig.usrp_sink_c_sptr_detail(self)

    def set_detail(self, *args, **kwargs):
        """set_detail(self, gr_block_detail_sptr detail)"""
        return _usrp_swig.usrp_sink_c_sptr_set_detail(self, *args, **kwargs)

    def name(self):
        """name(self) -> string"""
        return _usrp_swig.usrp_sink_c_sptr_name(self)

    def input_signature(self):
        """input_signature(self) -> gr_io_signature_sptr"""
        return _usrp_swig.usrp_sink_c_sptr_input_signature(self)

    def output_signature(self):
        """output_signature(self) -> gr_io_signature_sptr"""
        return _usrp_swig.usrp_sink_c_sptr_output_signature(self)

    def unique_id(self):
        """unique_id(self) -> long"""
        return _usrp_swig.usrp_sink_c_sptr_unique_id(self)

    def basic_block(self):
        """basic_block(self) -> gr_basic_block_sptr"""
        return _usrp_swig.usrp_sink_c_sptr_basic_block(self)

    def check_topology(self, *args, **kwargs):
        """check_topology(self, int ninputs, int noutputs) -> bool"""
        return _usrp_swig.usrp_sink_c_sptr_check_topology(self, *args, **kwargs)

usrp_sink_c_sptr_swigregister = _usrp_swig.usrp_sink_c_sptr_swigregister
usrp_sink_c_sptr_swigregister(usrp_sink_c_sptr)

usrp_sink_c_sptr.block = lambda self: usrp_sink_c_block (self)
usrp_sink_c_sptr.__repr__ = lambda self: "<gr_block %s (%d)>" % (self.name(), self.unique_id ())


def sink_c(*args, **kwargs):
  """
    sink_c(int which = 0, unsigned int interp_rate = 32, int nchan = 1, 
        int mux = -1, int fusb_block_size = 0, 
        int fusb_nblocks = 0, string fpga_filename = "", 
        string firmware_filename = "") -> usrp_sink_c_sptr
    """
  return _usrp_swig.sink_c(*args, **kwargs)
class usrp_sink_s_sptr(object):
    """Proxy of C++ boost::shared_ptr<(usrp_sink_s)> class"""
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    def __init__(self, *args): 
        """
        __init__(self) -> usrp_sink_s_sptr
        __init__(self,  p) -> usrp_sink_s_sptr
        """
        this = _usrp_swig.new_usrp_sink_s_sptr(*args)
        try: self.this.append(this)
        except: self.this = this
    def __deref__(self):
        """__deref__(self)"""
        return _usrp_swig.usrp_sink_s_sptr___deref__(self)

    __swig_destroy__ = _usrp_swig.delete_usrp_sink_s_sptr
    __del__ = lambda self : None;
    def set_interp_rate(self, *args, **kwargs):
        """set_interp_rate(self, unsigned int rate) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_set_interp_rate(self, *args, **kwargs)

    def set_nchannels(self, *args, **kwargs):
        """set_nchannels(self, int nchan) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_set_nchannels(self, *args, **kwargs)

    def set_mux(self, *args, **kwargs):
        """set_mux(self, int mux) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_set_mux(self, *args, **kwargs)

    def _real_determine_tx_mux_value(self, *args):
        """
        _real_determine_tx_mux_value(self, usrp_subdev_spec ss) -> int
        _real_determine_tx_mux_value(self, usrp_subdev_spec ss_a, usrp_subdev_spec ss_b) -> int
        """
        return _usrp_swig.usrp_sink_s_sptr__real_determine_tx_mux_value(self, *args)

    def set_tx_freq(self, *args, **kwargs):
        """set_tx_freq(self, int channel, double freq) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_set_tx_freq(self, *args, **kwargs)

    def dac_rate(self):
        """dac_rate(self) -> long"""
        return _usrp_swig.usrp_sink_s_sptr_dac_rate(self)

    def dac_freq(self):
        """dac_freq(self) -> long"""
        return _usrp_swig.usrp_sink_s_sptr_dac_freq(self)

    def interp_rate(self):
        """interp_rate(self) -> unsigned int"""
        return _usrp_swig.usrp_sink_s_sptr_interp_rate(self)

    def nchannels(self):
        """nchannels(self) -> int"""
        return _usrp_swig.usrp_sink_s_sptr_nchannels(self)

    def mux(self):
        """mux(self) -> int"""
        return _usrp_swig.usrp_sink_s_sptr_mux(self)

    def tx_freq(self, *args, **kwargs):
        """tx_freq(self, int channel) -> double"""
        return _usrp_swig.usrp_sink_s_sptr_tx_freq(self, *args, **kwargs)

    def nunderruns(self):
        """nunderruns(self) -> int"""
        return _usrp_swig.usrp_sink_s_sptr_nunderruns(self)

    def has_rx_halfband(self):
        """has_rx_halfband(self) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_has_rx_halfband(self)

    def has_tx_halfband(self):
        """has_tx_halfband(self) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_has_tx_halfband(self)

    def nddcs(self):
        """nddcs(self) -> int"""
        return _usrp_swig.usrp_sink_s_sptr_nddcs(self)

    def nducs(self):
        """nducs(self) -> int"""
        return _usrp_swig.usrp_sink_s_sptr_nducs(self)

    def _real_tune(self, *args, **kwargs):
        """_real_tune(self, int chan, db_base_sptr db, double target_freq, usrp_tune_result result) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr__real_tune(self, *args, **kwargs)

    def _real_pick_tx_subdevice(self):
        """_real_pick_tx_subdevice(self) -> usrp_subdev_spec"""
        return _usrp_swig.usrp_sink_s_sptr__real_pick_tx_subdevice(self)

    def db(self, *args):
        """
        db(self) -> db_base_sptr_vector_vector
        db(self, int which_side) -> db_base_sptr_vector
        db(self, int which_side, int which_dev) -> db_base_sptr
        """
        return _usrp_swig.usrp_sink_s_sptr_db(self, *args)

    def _real_selected_subdev(self, *args, **kwargs):
        """_real_selected_subdev(self, usrp_subdev_spec ss) -> db_base_sptr"""
        return _usrp_swig.usrp_sink_s_sptr__real_selected_subdev(self, *args, **kwargs)

    def fpga_master_clock_freq(self):
        """fpga_master_clock_freq(self) -> long"""
        return _usrp_swig.usrp_sink_s_sptr_fpga_master_clock_freq(self)

    def set_fpga_master_clock_freq(self, *args, **kwargs):
        """set_fpga_master_clock_freq(self, long master_clock)"""
        return _usrp_swig.usrp_sink_s_sptr_set_fpga_master_clock_freq(self, *args, **kwargs)

    def set_verbose(self, *args, **kwargs):
        """set_verbose(self, bool on)"""
        return _usrp_swig.usrp_sink_s_sptr_set_verbose(self, *args, **kwargs)

    READ_FAILED = _swig_property(_usrp_swig.usrp_sink_s_sptr_READ_FAILED_get)
    def write_eeprom(self, *args, **kwargs):
        """write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_write_eeprom(self, *args, **kwargs)

    def read_eeprom(self, *args, **kwargs):
        """read_eeprom(self, int i2c_addr, int eeprom_offset, int len) -> string"""
        return _usrp_swig.usrp_sink_s_sptr_read_eeprom(self, *args, **kwargs)

    def write_i2c(self, *args, **kwargs):
        """write_i2c(self, int i2c_addr, string buf) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_write_i2c(self, *args, **kwargs)

    def read_i2c(self, *args, **kwargs):
        """read_i2c(self, int i2c_addr, int len) -> string"""
        return _usrp_swig.usrp_sink_s_sptr_read_i2c(self, *args, **kwargs)

    def set_adc_offset(self, *args, **kwargs):
        """set_adc_offset(self, int which_adc, int offset) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_set_adc_offset(self, *args, **kwargs)

    def set_dac_offset(self, *args, **kwargs):
        """set_dac_offset(self, int which_dac, int offset, int offset_pin) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_set_dac_offset(self, *args, **kwargs)

    def set_adc_buffer_bypass(self, *args, **kwargs):
        """set_adc_buffer_bypass(self, int which_adc, bool bypass) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_set_adc_buffer_bypass(self, *args, **kwargs)

    def set_dc_offset_cl_enable(self, *args, **kwargs):
        """set_dc_offset_cl_enable(self, int bits, int mask) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_set_dc_offset_cl_enable(self, *args, **kwargs)

    def serial_number(self):
        """serial_number(self) -> string"""
        return _usrp_swig.usrp_sink_s_sptr_serial_number(self)

    def daughterboard_id(self, *args, **kwargs):
        """daughterboard_id(self, int which_side) -> int"""
        return _usrp_swig.usrp_sink_s_sptr_daughterboard_id(self, *args, **kwargs)

    def write_atr_tx_delay(self, *args, **kwargs):
        """write_atr_tx_delay(self, int value) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_write_atr_tx_delay(self, *args, **kwargs)

    def write_atr_rx_delay(self, *args, **kwargs):
        """write_atr_rx_delay(self, int value) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_write_atr_rx_delay(self, *args, **kwargs)

    def set_pga(self, *args, **kwargs):
        """set_pga(self, int which_amp, double gain_in_db) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_set_pga(self, *args, **kwargs)

    def pga(self, *args, **kwargs):
        """pga(self, int which_amp) -> double"""
        return _usrp_swig.usrp_sink_s_sptr_pga(self, *args, **kwargs)

    def pga_min(self):
        """pga_min(self) -> double"""
        return _usrp_swig.usrp_sink_s_sptr_pga_min(self)

    def pga_max(self):
        """pga_max(self) -> double"""
        return _usrp_swig.usrp_sink_s_sptr_pga_max(self)

    def pga_db_per_step(self):
        """pga_db_per_step(self) -> double"""
        return _usrp_swig.usrp_sink_s_sptr_pga_db_per_step(self)

    def _write_oe(self, *args, **kwargs):
        """_write_oe(self, int which_side, int value, int mask) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr__write_oe(self, *args, **kwargs)

    def write_io(self, *args, **kwargs):
        """write_io(self, int which_side, int value, int mask) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_write_io(self, *args, **kwargs)

    def read_io(self, *args, **kwargs):
        """read_io(self, int which_side) -> int"""
        return _usrp_swig.usrp_sink_s_sptr_read_io(self, *args, **kwargs)

    def write_atr_mask(self, *args, **kwargs):
        """write_atr_mask(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_write_atr_mask(self, *args, **kwargs)

    def write_atr_txval(self, *args, **kwargs):
        """write_atr_txval(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_write_atr_txval(self, *args, **kwargs)

    def write_atr_rxval(self, *args, **kwargs):
        """write_atr_rxval(self, int which_side, int value) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_write_atr_rxval(self, *args, **kwargs)

    def write_aux_dac(self, *args, **kwargs):
        """write_aux_dac(self, int which_side, int which_dac, int value) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_write_aux_dac(self, *args, **kwargs)

    def read_aux_adc(self, *args, **kwargs):
        """read_aux_adc(self, int which_side, int which_adc) -> int"""
        return _usrp_swig.usrp_sink_s_sptr_read_aux_adc(self, *args, **kwargs)

    def converter_rate(self):
        """converter_rate(self) -> long"""
        return _usrp_swig.usrp_sink_s_sptr_converter_rate(self)

    def _set_led(self, *args, **kwargs):
        """_set_led(self, int which_led, bool on) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr__set_led(self, *args, **kwargs)

    def _write_fpga_reg(self, *args, **kwargs):
        """_write_fpga_reg(self, int regno, int value) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr__write_fpga_reg(self, *args, **kwargs)

    def _read_fpga_reg(self, *args, **kwargs):
        """_read_fpga_reg(self, int regno) -> int"""
        return _usrp_swig.usrp_sink_s_sptr__read_fpga_reg(self, *args, **kwargs)

    def _write_fpga_reg_masked(self, *args, **kwargs):
        """_write_fpga_reg_masked(self, int regno, int value, int mask) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr__write_fpga_reg_masked(self, *args, **kwargs)

    def _write_9862(self, *args, **kwargs):
        """_write_9862(self, int which_codec, int regno, unsigned char value) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr__write_9862(self, *args, **kwargs)

    def _read_9862(self, *args, **kwargs):
        """_read_9862(self, int which_codec, int regno) -> int"""
        return _usrp_swig.usrp_sink_s_sptr__read_9862(self, *args, **kwargs)

    def _write_spi(self, *args, **kwargs):
        """_write_spi(self, int optional_header, int enables, int format, string buf) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr__write_spi(self, *args, **kwargs)

    def _read_spi(self, *args, **kwargs):
        """_read_spi(self, int optional_header, int enables, int format, int len) -> string"""
        return _usrp_swig.usrp_sink_s_sptr__read_spi(self, *args, **kwargs)

    def _real_pick_subdev(self, *args, **kwargs):
        """_real_pick_subdev(self, __dummy_3__ candidates = std::vector< int >(0)) -> usrp_subdev_spec"""
        return _usrp_swig.usrp_sink_s_sptr__real_pick_subdev(self, *args, **kwargs)

    def history(self):
        """history(self) -> unsigned int"""
        return _usrp_swig.usrp_sink_s_sptr_history(self)

    def output_multiple(self):
        """output_multiple(self) -> int"""
        return _usrp_swig.usrp_sink_s_sptr_output_multiple(self)

    def relative_rate(self):
        """relative_rate(self) -> double"""
        return _usrp_swig.usrp_sink_s_sptr_relative_rate(self)

    def start(self):
        """start(self) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_start(self)

    def stop(self):
        """stop(self) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_stop(self)

    def detail(self):
        """detail(self) -> gr_block_detail_sptr"""
        return _usrp_swig.usrp_sink_s_sptr_detail(self)

    def set_detail(self, *args, **kwargs):
        """set_detail(self, gr_block_detail_sptr detail)"""
        return _usrp_swig.usrp_sink_s_sptr_set_detail(self, *args, **kwargs)

    def name(self):
        """name(self) -> string"""
        return _usrp_swig.usrp_sink_s_sptr_name(self)

    def input_signature(self):
        """input_signature(self) -> gr_io_signature_sptr"""
        return _usrp_swig.usrp_sink_s_sptr_input_signature(self)

    def output_signature(self):
        """output_signature(self) -> gr_io_signature_sptr"""
        return _usrp_swig.usrp_sink_s_sptr_output_signature(self)

    def unique_id(self):
        """unique_id(self) -> long"""
        return _usrp_swig.usrp_sink_s_sptr_unique_id(self)

    def basic_block(self):
        """basic_block(self) -> gr_basic_block_sptr"""
        return _usrp_swig.usrp_sink_s_sptr_basic_block(self)

    def check_topology(self, *args, **kwargs):
        """check_topology(self, int ninputs, int noutputs) -> bool"""
        return _usrp_swig.usrp_sink_s_sptr_check_topology(self, *args, **kwargs)

usrp_sink_s_sptr_swigregister = _usrp_swig.usrp_sink_s_sptr_swigregister
usrp_sink_s_sptr_swigregister(usrp_sink_s_sptr)

usrp_sink_s_sptr.block = lambda self: usrp_sink_s_block (self)
usrp_sink_s_sptr.__repr__ = lambda self: "<gr_block %s (%d)>" % (self.name(), self.unique_id ())


def sink_s(*args, **kwargs):
  """
    sink_s(int which = 0, unsigned int interp_rate = 32, int nchan = 1, 
        int mux = -1, int fusb_block_size = 0, 
        int fusb_nblocks = 0, string fpga_filename = "", 
        string firmware_filename = "") -> usrp_sink_s_sptr
    """
  return _usrp_swig.sink_s(*args, **kwargs)
# Allow subdev_spec to be tuple
def __selected_subdev(self, subdev_spec):
  ss = usrp_subdev_spec(subdev_spec[0], subdev_spec[1])
  return self._real_selected_subdev(ss)

# Allow subdev_spec to be tuple
def __determine_tx_mux_value(self, subdev_spec, subdev_spec_=None):
    ss = usrp_subdev_spec(subdev_spec[0], subdev_spec[1])
    if subdev_spec_ is None: return self._real_determine_tx_mux_value(ss)
    ss_ = usrp_subdev_spec(subdev_spec_[0], subdev_spec_[1])
    return self._real_determine_tx_mux_value(ss, ss_)

# Allow subdev_spec to be tuple
def __determine_rx_mux_value(self, subdev_spec, subdev_spec_=None):
    ss = usrp_subdev_spec(subdev_spec[0], subdev_spec[1])
    if subdev_spec_ is None: return self._real_determine_rx_mux_value(ss)
    ss_ = usrp_subdev_spec(subdev_spec_[0], subdev_spec_[1])
    return self._real_determine_rx_mux_value(ss, ss_)

# Allow subdev_spec to be tuple
def __pick_subdev(self, candidates=[]):
    ss = self._real_pick_subdev(candidates)
    return (ss.side, ss.subdev)

# Allow subdev_spec to be tuple
def __pick_tx_subdevice(self):
    ss = self._real_pick_tx_subdevice()
    return (ss.side, ss.subdev)

# Allow subdev_spec to be tuple
def __pick_rx_subdevice(self):
    ss = self._real_pick_rx_subdevice()
    return (ss.side, ss.subdev)

# Make return tune_result or None on failure
def __tune(self, chan, db, target_freq):
    tr = usrp_tune_result()
    r = self._real_tune(chan, db, target_freq, tr)
    if r:
        return tr
    else:
        return None

# Allow to be called as a free function
def tune(u, chan, subdev, target_freq):
    return u.tune(chan, subdev, target_freq)

# Allow to be called as free function
def determine_tx_mux_value(u, subdev_spec, subdev_spec_=None):
    return u.determine_tx_mux_value(subdev_spec, subdev_spec_)

# Allow to be called as free function
def determine_rx_mux_value(u, subdev_spec, subdev_spec_=None):
    return u.determine_rx_mux_value(subdev_spec, subdev_spec_)

# Allow to be called as free function
def selected_subdev(u, subdev_spec):
    return u.selected_subdev(subdev_spec)

# Allow to be called as free function
def pick_subdev(u, candidates=[]):
    return u.pick_subdev(candidates);

# Allow to be called as free function
def pick_tx_subdevice(u):
    return u.pick_tx_subdevice();

# Allow to be called as free function
def pick_rx_subdevice(u):
    return u.pick_rx_subdevice();

# Jam into Python objects
usrp_sink_c_sptr.determine_tx_mux_value   = __determine_tx_mux_value
usrp_sink_s_sptr.determine_tx_mux_value   = __determine_tx_mux_value

usrp_source_c_sptr.determine_rx_mux_value = __determine_rx_mux_value
usrp_source_s_sptr.determine_rx_mux_value = __determine_rx_mux_value

usrp_sink_c_sptr.selected_subdev          = __selected_subdev
usrp_sink_s_sptr.selected_subdev          = __selected_subdev
usrp_source_c_sptr.selected_subdev        = __selected_subdev
usrp_source_s_sptr.selected_subdev        = __selected_subdev

usrp_sink_c_sptr.tune                     = __tune
usrp_sink_s_sptr.tune                     = __tune
usrp_source_c_sptr.tune                   = __tune
usrp_source_s_sptr.tune                   = __tune

usrp_sink_c_sptr.pick_subdev              = __pick_subdev
usrp_sink_s_sptr.pick_subdev              = __pick_subdev
usrp_source_c_sptr.pick_subdev            = __pick_subdev
usrp_source_s_sptr.pick_subdev            = __pick_subdev

usrp_sink_c_sptr.pick_tx_subdevice        = __pick_tx_subdevice
usrp_sink_s_sptr.pick_tx_subdevice        = __pick_tx_subdevice
usrp_source_c_sptr.pick_rx_subdevice      = __pick_rx_subdevice
usrp_source_s_sptr.pick_rx_subdevice      = __pick_rx_subdevice




